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Filtering by: Graduation year 2002 Remove constraint Graduation year: 2002 Advisor Mayaram, Kartikeya Remove constraint Advisor: Mayaram, Kartikeya

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  • Algorithms and simulators for coupled device/circuit simulation

    Creator:
    Dudar, Taras
    Abstract:
    Algorithms and simulators comprised of SPICE3 as a circuit level simulator and two device simulators EOFLOW and PROPHET for accurate simulation of new types of devices are presented in this thesis. An integration of EOFLOW with SPICE3 creates a capability for efficient simulation of a system containing interconnected electroosmotic flow...
    Resource Type:
    Masters Thesis
    Full Text:
    Master of Science in Electrical and Computer Engineering presented on December 11, 2002. Title

  • Substrate coupling macromodel for lightly doped CMOS processes

    Creator:
    Koteeswaran, Mohanalakshmi
    Abstract:
    A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of...
    Resource Type:
    Masters Thesis
    Full Text:
    degree of Master of Science in Electrical and Computer Engineering presented on September 16, 2002

  • Analysis and design of CMOS RF LNAs with ESD protection

    Creator:
    Chandrasekhar, Vinay
    Abstract:
    An analysis that accounts for the effect of standard electrostatic discharge (ESD) structures on critical LNA specifications of noise figure, input matching and gain is presented. It is shown that the ESD structures degrade LNA performance particularly for higher frequency applications. Two LNAs, one with ESD protection and one without,...
    Resource Type:
    Masters Thesis
    Full Text:
    of Master of Science in Electrical and Computer Engineering presented on April 1, 2002. Title

  • Prediction of phase noise and jitter in ring oscillators

    Creator:
    Barton, Nathen
    Abstract:
    This thesis presents distinctly different methods of accurately predicting phase noise and absolute jitter in ring oscillators. The phase noise prediction methods are the commercially available SpectreRF and isf_tool, a simulator developed in this work from the Hajimiri and Lee theory of phase noise. Absolute jitter due to deterministic supply...
    Resource Type:
    Masters Thesis
    Full Text:
    Master of Science in Electrical and Computer Engineering presented on March 5. 2002. Title: Prediction

  • Substrate noise coupling in ring oscillator-based phase locked loops

    Creator:
    Shreeve, Robert
    Abstract:
    In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35 μm CMOS process. Since the...
    Resource Type:
    Masters Thesis

  • Layout dependent and bias independent scalable substrate model for RF MOSFETs

    Creator:
    Suravarapu, Ravikanth
    Abstract:
    The dependence of the substrate resistance, R[subscript sub], for MOS transistor RF modeling on transistor biasing and layout is studied from device simulations and measurements. Though R[subscript sub] is found to be bias dependent, the error incurred by assuming a constant value equal to the DC resistance is not significant....
    Resource Type:
    Masters Thesis

  • An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

    Creator:
    Farahbakhshian, Farhad
    Abstract:
    An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to swing below ground and above the supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
    Resource Type:
    Masters Thesis
    Full Text:
    challenge in ultra low power design,” in IEEE Int. Solid-State Circuit Conf., Feb. 2002, pp. 200–201. [3] P

  • Ultra-low power receivers for wireless sensor networks

    Creator:
    Ayers, James S.
    Abstract:
    In wireless sensor network applications, low-power operation of the wireless receiver is critical. To address this need an ultra-low power Binary Frequency Shift Keying (BFSK) receiver using the super-regenerative architecture is developed. A prototype receiver is built and tested for operation in the 900 MHz ISM band. Lab measurements show...
    Resource Type:
    Dissertation
    Full Text:
    ,I 1 24 [22] 0.35 µm 2002 900 MHz L,M N/R N/R [23] 0.18 µm 2002 2.4 GHz L,M N/R N/R [24] 0.18 µm

  • Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

    Creator:
    Sharma, Ajit
    Abstract:
    This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
    Resource Type:
    Masters Thesis
    Full Text:
    Inc. for a chance to intern at Micro Systems Engineering during the summer of 2002. I really learned

  • Silencer! : a tool for substrate noise coupling analysis

    Creator:
    Birrer, Patrick
    Abstract:
    This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different...
    Resource Type:
    Masters Thesis