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Filtering by: Creator Traylor, Roger L. Remove constraint Creator: Traylor, Roger L. Non-Academic Affiliation Oregon State University. Graduate School Remove constraint Non-Academic Affiliation: Oregon State University. Graduate School

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  • A token caching waiting-matching unit for tagged-token dataflow computers

    Creator:
    Traylor, Roger L.
    Abstract:
    Computers using the tagged-token dataflow model are among the best candidates for delivering extremely high levels of performance required in the future. Instruction scheduling in these computers is determined by associatively matching data-bearing tokens in a Waiting-Matching Unit (W-M unit). At the W-M unit, incoming tokens with matching contexts are...
    Resource Type:
    Masters Thesis
    Full Text:
    dataflow computers AN ABSTRACT OF THE THESIS OF Roger L. Traylor for the degree of Master of Science in

  • Development test suite for FPGA TekBot learning platform

    Creator:
    Lai, Gerald
    Abstract:
    As the Tekbots program expands into senior and graduate level classes at Oregon State University, so does the need arise for more complex learning platforms. These complex hardware platforms cannot be adequately tested in a manufacturing environment as we have done previously. Also, due to their complexity, these platforms require...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Roger L. Traylor As the TekBots® program expands into senior and graduate level classes

  • A comprehensive integration of first year engineering education

    Creator:
    Shuman, Matthew W.
    Abstract:
    Retention of engineering students is a problem for many universities, especially during the first year. The problem of introducing students to engineering while increasing retention rates has recently been addressed by many different universities. Implementing novel lab structures, adjusting the lecture to incorporate more effective teaching techniques, and using orientation...
    Resource Type:
    Masters Thesis
    Full Text:
    Abstract approved: Roger Traylor Retention of engineering students is a problem for many

  • An efficient switched capacitor buck-boost voltage regulator using delta-sigma control loop

    Creator:
    Rao, Arun
    Abstract:
    Voltage converters or charge pumps find their use in many circuits. They are extensively used in hand held devices as cell phones, pagers, PDA's and laptops. Some of the important issues relating to design of voltage regulators for handheld devices are size, efficiency and noise. Another important factor to be...
    Resource Type:
    Masters Thesis
    Full Text:
    acknowledge the other members of my committee, Roger Traylor and Dr. Prasad Tadepalli for taking the time and

  • Substrate coupling macromodel for lightly doped CMOS processes

    Creator:
    Koteeswaran, Mohanalakshmi
    Abstract:
    A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of...
    Resource Type:
    Masters Thesis
    Full Text:
    would like to thank Dr. Michael Quinn and Prof. Roger Traylor for taking interest in my work and for

  • Ultra-low energy digital controller for battery-free wireless sensor network nodes

    Creator:
    Nasroullahi, Mohsen
    Abstract:
    This thesis presents a low-energy application specific digital controller for a battery-free 2.4 GHz wireless sensor network (WSN) node. The digital controller has been designed and fabricated in a standard 0.13 μm CMOS and implements a simple protocol for WSNs. Techniques such as supply voltage reduction and power gating have...
    Resource Type:
    Masters Thesis
    Full Text:
    instructors and professors, especially Roger Traylor, for teaching, guiding, mentoring and motivating me

  • Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

    Creator:
    Hanken, Christopher
    Abstract:
    Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...
    Resource Type:
    Masters Thesis

  • Sensor communication network within a desktop computer using the DC powerline

    Creator:
    Bahniuk, Eileen Kei
    Abstract:
    Powerline communication (PLC), is becoming a more commonplace method for data transmission, however it is still a very new medium for data transmission, and international standards for powerline communication are still in the process of being developed and established. PLC can provide a means of simplifying the device connectivity to...
    Resource Type:
    Masters Thesis
    Full Text:
    letter for graduate school; the GCR David Hackleman and committee members Thinh Ngyuen, and Roger

  • TIMR : Time Interleaved Multi Rail

    Creator:
    Ruggeri, Thomas L.
    Abstract:
    This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail....
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Thomas L. Ruggeri for the

  • Optimizing performance/watt of embedded SIMD multiprocessors through a priori application guided power scheduling

    Creator:
    Albright, Ryan K.
    Abstract:
    A method for improving performance/watt of an embedded single-instruction multiple-data (SIMD) architecture using application-guided a priori scheduling of hardware resources is presented. A multi-core architectural simulator is adopted that accurately estimates power, performance, and utilization of various processor components (logic, interconnect and memory). A greedy search is then performed on...
    Resource Type:
    Masters Thesis
    Full Text:
    my advisor Dr. Patrick Chiang. I would also like to thank my committee: Dr. Terri Fiez, Roger