Scaling the supply voltage into the sub/near-threshold domain is one of the most effective methods for improving the energy efficiency of next-generation electronic microsystems. Unfortunately, the relationship between low-voltage operation and radiation-induced soft error rate is not widely known, as little research has been previously performed and reported for soft-error...
As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links. However, the increase in data-rate is sustainable only if the I/O energy efficiency improves as well. This dissertation explores several techniques to enable high-speed links...
With the evolving popularity of new computing platforms such as Ultrabooks, Tablets, and Smart Phones, and the shift to multi-core computing, power is now the key performance limiter, a departure from the traditional frequency limitation. As such, increasingly low-power design solutions feature prominently in early architectural and design space exploration...
Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off...
The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of...
Constant and reliable health monitoring can help doctors provide higher quality
health care to meet the growing needs of the medical industry. The advent of
cloud computing has enabled low-cost sensor devices that can process their data
in real-time without powerful onboard hardware. Using an Android smartphone,
medical data can...
This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail....
The problem of footstep level resolution indoor path tracking and gait velocity
lacks a good solution. The current solutions are either prohibitively expensive [4],
extremely invasive to deploy [1], or too inaccurate to achieve the sub meter level
resolution required to track foot paths. By combining existing pedestrian dead
reckoning...
The prevalence of Internet-of-Things (IoT) applications leads to an increasing focus on the design and optimization of sensor nodes. Battery lifetime and associated costs of battery replacement often limits the long term operation and viability of sensor nodes. RF wireless energy harvesting on the other hand can be appealing since...
The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die area are some of the most important criteria for successful WBAN implementations. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in...
The rapid scaling of network bandwidth and data center throughput has motivated the wide adoption of high speed transceivers. Silicon photonics (Si-Photonic) is one of the most promising techniques to realize tightly integrated optical transceivers for next-generation high speed I O standards. This dissertation focuses on the design techniques of...
Recent sensor System-on-Chips (SoC) have enabled significant advances in energy-efficiency by incorporating various micro-powered building blocks. Unfortunately, most of these sensor systems do not address the high power cost associated with data storage and transmission, which in some cases vastly exceeds the power consumed by the rest of the SoC....
The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
This work describes the development of an accurate, low-cost, expandable and wearable health and activity monitoring platform. Wearable monitors used to track physical activity are becoming an increasingly popular and effective way to combat our dangerously sedentary lifestyles. Unfortunately most existing wearable solutions are either costly, inaccurate or cumbersome. The...
Energy consumption is one of the primary bottlenecks to both large and small scale modern compute platforms. Reducing the operating voltage of digital circuits to voltages where the supply voltage is near or below the threshold of the transistors has recently gained attention as a method to reduce the energy...
For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
The proliferation of body worn autometric devices has been enabled by advances in low-power electronics and fueled by the quantified-self movement. These devices range in complexity from pedometers to clinical vital sign measurement. They all share the same drawback, typically the most expensive and heaviest component, the battery. The future...
A method for improving performance/watt of an embedded single-instruction multiple-data (SIMD) architecture using application-guided a priori scheduling of hardware resources is presented. A multi-core architectural simulator is adopted that accurately estimates power, performance, and utilization of various processor components (logic, interconnect and memory). A greedy search is then performed on...
This work presents improvements to a multi-core performance/power simulator. The improvements which include updated power models, voltage scaling aware models, and an application specific benchmark, are done to increase the accuracy of power models under voltage and frequency scaling. Improvements to the simulator enable more accurate design space exploration for...
High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most...
Short-range wireless communications continually attract interest from both industry and academia, and it is changing our life in every aspect in the last decade. The design of wireless transceivers is the bottleneck for variety applications, due to RF modeling inaccuracy, stringent FCC regulations over the transmitted power spectrum, interference, multi-path...
Ultra-wideband (UWB) radio has become an attractive alternative for wireless communications due to the robustness to multipath fading, low power transmission, mostly-digital implementation, and low cost. Furthermore, short-range, high data-rates applications are possible with UWB radios due to the wide spectral
allocations at 3.1 - 10.6 GHz.
This thesis presents...
Various applications like wireless UWB communication, fast data acquisition systems and digital storage oscilloscopes needs ADCs with instantaneous input signal bandwidth from 0.1-40 GigaHertz range with 6-10 bits of resolution -- a challenging task and an impressive goal to achieve. Flash ADCs have been conventionally employed to achieve these goals...
Modern wireless System-on-Chips (SoCs), such as mobile handsets, sensor networks, and mm-wave systems, integrate an entire RF system on a single CMOS chip. Such highly complex systems require significant on-chip digital signal processing to help improve the performance of highly sensitive analog/RF components. The IC
market being competitive, the ability...
Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result...