This thesis describes the adder to be used with the Galaxy computer, which is to be constructed at Oregon State University.
The need for faster, more reliable adders is discussed
along with previous adder designs related to the
Galaxy Fast Carry Adder.
Both the logical design and circuit design of...
The concept of combining arithmetic and memory capability on
a single semiconductor chip has become practical from a system's
viewpoint through the decreased cost of semiconductor memories and
high circuit densities achieved through large scale integration. This
paper describes a model for studying the feasibility of such systems.
An arithmetic-memory...
Research in digital computers takes two paths: one uses the
computer as a tool to reach certain objectives; on the other, the computer
itself is the object of research. The NEBULA computer was
built with the latter in mind. The system design and logical design
are described here in detail....
Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm.
A mixed-signal IC implementation has been chosen for...
Multi-stage delta-sigma (ΔΣ) architectures, commonly known as MASH, are the preferred choice for analog-to-digital converters (ADCs) used in broadband communication applications, where high-resolution (above 14 bits) and high-bandwidth (several MHz) performances are required. Current state-of-the-art designs are capable of as much as 5-MS/s output data rates with 90-dB SNR. However,...
Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common...
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts.
In this thesis, a wideband low-power CT ΔΣ modulator for next generation...
In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless and wireline communication applications.
So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s)....
Scaling of CMOS technology has progressed relentlessly for the past several
decades. In order for this unprecedented scaling to benefit the performance of
large digital systems, the communication bandwidth between integrated circuits
(ICs) must scale accordingly. However, interconnect technology does not scale as
aggressively, making communication between chips the major...
