Engineering students spend a significant amount of their undergraduate careers focused on technical theory and practice. This intensive student prepares them for their technical challenges in the future. This training is so intense that often the more 'soft skills' such as communication, leadership, design, and troubleshooting are left out or...
Hardware weekend (HWeekend) is a free 30-hour hardware development event sponsored by the College of Engineering, College of Business, and Inventors Enterprise wherein students work together in small teams to create a marketable project they can demonstrate and pitch to judges at the end of the weekend. Unlike similar events,...
The Jetson Artificial Intelligence Tool chain (JAI-TC) is a set of packages, APIs and libraries for Artificial Intelligence applications to be deployed on the NVidia SOC, Jetson TX2. JAI-TC automates the installation of these items allowing for a wider set of users to leverage these technologies. Prior to this, the...
This project is a custom output stage for a two-channel signal source design project at Oregon State. Starting in January, I began leading a team tasked with the development of an arbitrary waveform generator via the CreateIT Collaboratory at OSU. Undergraduate students interview into the CreateIT Collaboratory and are assigned...
This thesis is a development of two sets of equations predicting the switching times of a saturated transistor. The first set of equations defines the rise, storage, and fall times at a single operating point where the transistor beta, cutoff frequency and collector capacitance are known. The second set of...
This thesis describes the adder to be used with the Galaxy computer, which is to be constructed at Oregon State University.
The need for faster, more reliable adders is discussed
along with previous adder designs related to the
Galaxy Fast Carry Adder.
Both the logical design and circuit design of...
The operation of a tunnel-diode delay-line memory cell is
examined in some detail, and a digital computer program which
approximately simulates the operation of this memory cell is developed.
The data from the computer simulation is compared with the
available experimental data and found to agree very closely for clock...
This thesis
is concerned
with the
problems
which
need
consideration
when
designing
a
nanosecond
pulse
generator
having
a
repeatable
pulse
width
and
amplitude
output.
The
basic
circuit
is
first
presented
and
analyzed
and
the
reasons
for
wide
variations
in
pulse
width
with
replacement
of
transistors
are
pointed
out.
To
make...
This paper describes an inverter design which provides voltage
regulation against variations in both the input voltage and load impedance.
This design modifies the so-called parallel inverter, which
consists of two silicon controlled rectifiers (SCRs) operating in a
push-pull arrangement, to include a third regulating SCR. This
regulating SCR is...