The new CMOS folded source-coupled logic (FSCL)
technique intended for mixed-mode integrated circuits has
been designed. It has advantages over conventional CMOS
circuit in terms of reduced current spike, circuit delay,
logic flexibility, and layout density. A simple CPU
implemented in 2 μm CMOS technology with a 5.0 volt supply...
Advances in VLSI array processing have led to many new
parallel structures for real-time Digital Signal Processing (DSP)
applications. Among all the architectures, systolic arrays have played
an important role because systolic arrays have regular, local
interconnections with modular structure. In ordinary systolic arrays,
however, all processing operations and data...
The purpose of this thesis is to apply the Canonical Correlation
Analysis (CCA) which belongs to the parametric methods for power
spectral estimation in the environments of either white noise or
colored noise. It is shown that optimal state space variables
belong to the range space of the canonical vectors...
The resolution of analog-to-digital converters can be distinguished as absolute resolution, or average resolution. This study reviews average resolution enhancement techniques and proposes a method which is particularly applicable as a low-cost modification to a high-speed waveform acquisition system. This method uses oversampling combined with computationally simple digital filtering to...
Digital signal and image processing and other real time
applications involve simple but large amounts of
computations. These problems have an enormous amount of
inherent parallelism and demand high speed computation.
Conventional computers do not possess these characteristics
and this had led to the development of new architectural
concepts. Among...
This thesis describes the development of a flash analog-to-digital converter based on
current-mode technique. The advantages of current -mode technique are higher speed,
smaller chip area, and simple division of reference current based on current mirror. A
current-mode comparator is designed consisting of a cascode current mirror and a
current...
Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays are synthesized by finding timing and allocation functions which transform index points in the recurrences into points in a space-time domain. The problem of scheduling...
Fully efficient systolic arrays for the solution of Toeplitz
matrices using Schur algorithm [1] have been obtained. By applying
clustering mapping method [2], the complexity of the algorithm is
0(n) and it requires n/2 processing elements as opposed to n
processing elements developed elsewhere [1].
The motivation of this thesis...
A series of complex digital blocks have been designed and fabricated using the newly
developed current-mode differential CMOS logic family viz. the Folded Source-Coupled
Logic ( FSCL ). The main feature of this logic family is the low current spikes generated
during the switching transitions ( at least 2 orders...