To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the floating switch dead zone, reduced SNR, and reduced ...

Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a varie ...

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Previous simulations of the Martian atmosphere have shown how topography acts to confine the low-level Hadley cell flow into intense jets on the eastern flanks of Tharsis and Syrtis Major. We now conduct detailed studies ...

Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fun ...

High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of th ...

In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to ...

This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the dire ...