Bai, Rui; Wang, Jingguang; Xia, Lingli; Zhang, Feng; Yang, Zongren; Hu, Weiwu; Chiang, Patrick (IEEE-Institute of Electrical and Electronics Engineers, 2011-12)
Current multi-gigahertz ADC performance is
limited by the sampling clock timing jitter. This paper describes
the effects of clock transition time on the spurious-free dynamic
range (SFDR) of a CMOS T/H circuit. A sign ...