http://hdl.handle.net/1957/7302 2013-05-25T00:34:37Z http://hdl.handle.net/1957/38725 Modeling and analysis of spur structure of digital-to-time conversion based frequency synthesizers Talwalkar, Sumit A. Frequency synthesizers are critical components of all communication systems. This thesis considers the issue of undesirable frequency spurs of a relatively recent type of frequency synthesis architecture called digital-to-time conversion (DTC). The DTC-based frequency synthesis architecture has important performance benefits over older frequency synthesizers, such as fast frequency switching, large frequency range and fine frequency resolution. A DTC-based frequency synthesizer requires less power than a traditional direct synthesis based synthesizer with comparable frequency range, resolution and switching time. The DTC architecture is also easily scalable to newer low-cost digital complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) fabrication technologies. However, the DTC architecture suffers from an important undesirable characteristic: sub-harmonic spurious tones, hereafter, referred to as spurs. Spurs have undesirable effects in both the transmitter and the receiver. In a transmitter, spurs create an out-of-band emission of power that may breach the spectral emission mask set by regulatory agencies to enable co-existence of multiple transmitters in a crowded frequency spectrum. In a receiver, an inopportune-located spur in the local oscillator (LO) signal can mix an out-of-band strong interfering signal into the baseband on top of a mixed-down weak desirable signal. Unlike harmonic spurs that are known to be at multiples of the carrier frequency, sub-harmonic spurs are especially problematic as they have been difficult to predict as part of the design process. In fact, the spur patterns for most pairs of closely placed desired output frequencies for a DTC-based frequency synthesizer are seemingly unrelated. While one output frequency setting might have an output spectrum with only a few spurs, many other close-by output frequency settings might have output spectra with many weaker spurs. The primary contribution of this thesis is the development of spur creation models and analysis tools that can predict spur spectrum and spur power levels for a DTC-based frequency synthesizer. This is an important contribution for assuring achievable performance of frequency synthesizer during the design process. The modeling approach has been successful in accounting of more than 99% of spur spectral locations. Predicted power levels for more than 95% are within 10 dB of actual fabricated DTC-based frequency synthesizer ICs. The results developed in this thesis allow for an understanding of the relationship between spur patterns for different selected output frequencies. In the research reported in this thesis, the spur spectrum for a selected output frequency is shown to be due to periodic occurrences of errors in the locations of rising and falling edges of the output signal. Error sequences for different selected output frequencies are shown to be related in a way that can be exploited by application of the axis-scaling property of the Discrete Fourier Transform (DFT). The axis-scaling property of the DFT relates the transforms of two sets of sequences that are predictably permutated versions of each other. Their respective transforms are also (differently) permutated versions of each other. One key insight made in this thesis is the discovery that the time-domain errors for all output frequencies can be classified into a very small number of error sequence classes. All error sequences within a class are shown to be predictable permutations of each other. This insight along with the DFT axis-scaling property permits the respective spur spectra to be classified into error spectra classes. All error spectra within a spur spectra class are predictable permutations of each other. There are two sources of edge errors: quantization error and buffer delay errors. This classification of spur spectra to a few classes is shown to be possible for both sources of errors. In this thesis, the case of quantization-only error is considered first. The analysis is then extended to the case when both sources of error are present. As a result of the modeling and analytical techniques developed for spur spectra classification described in this thesis, design tools have been created to predict the spur spectra of DTC-based synthesizer designs for all possible selected output frequencies. Graduation date: 2013 2013-05-21T00:00:00Z http://hdl.handle.net/1957/38709 Linearizing techniques for voltage controlled oscillator based analog to digital converters Rao, Sachin B. Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based ADCs behave like an open-loop continuous time ΔΣ modulator and achieve excellent resolution by first order noise shaping the quantization error. However, the SNDR of an open-loop VCO-based ADC is severely distortion limited by the voltage-to-frequency tuning characteristics of the VCO. This work examines various techniques that have already been proposed to overcome the VCO tuning non-linearity problem. Two new VCO-based ADC architectures, that overcome the limitations of the conventional approaches, are proposed. In the first approach, the ADC is linearized by forcing the VCO to operate at only two operating points using a front-end two level modulator. With this technique, the linearity is improved without using either a multi-bit feedback DAC or calibration. Fabricated in a 90 nm CMOS process, the prototype ADC achieves better than 71 dB SFDR and 59.1 dB SNDR in 8 MHz signal bandwidth while consuming 4.3 mW power. The ADC achieves a figure of merit of 366 fJ/conv-step, which is comparable with other state of the art time based ADCs. In the second approach, the need for a front-end two level modulator is obviated using linearizers, which introduce an inverse of VCO’s voltage to frequency characteristics in the signal path. A deterministic digital calibration unit runs continuously in the background and builds the inverse voltage to frequency transfer function. Implemented in a 90nm CMOS process, this on-chip calibration improves SFDR of the prototype ADC from 46 dB to more than 83 dB. The ADC consumes 4.1 mW power and achieves 73.9 dB SNDR in 5 MHz signal bandwidth resulting in an excellent figure of merit of 101 fJ/conv-step. Graduation date: 2013; Access restricted to the OSU Community at author's request from May 22, 2013 - May 22, 2015 2013-05-13T00:00:00Z http://hdl.handle.net/1957/38561 Helping end-user programmers help themselves : the idea garden approach Cao, Chen End-user programmers face many barriers in programming. Research has seen many programming environments that attempted to lower or remove the barriers but despite these efforts, empirical studies continue to report barriers users face. To investigate this issue, we took a theory-informed approach. Using theories from design, creativity, and problem solving as a lens, we examined end-user programmers' programming obstacles to derive design implications. Synthesizing the implications, we proposed an Idea Garden approach for creating problem-solving support in existing end-user programming environments aimed at helping users help themselves. This approach focuses on delivering problem-solving strategies and programming knowledge in the context of users' work to help them overcome barriers. We developed a proof-of-concept prototype of an Idea Garden for the CoScripter environment. Results from empirical studies of the prototype were encouraging: not only was the Idea Garden able to help users overcome barriers, learn relevant programming and strategies, but such learning persisted with users so that they were able to apply it toward problem-solving new tasks without further help from the Idea Garden. We conclude by providing recommendations to researchers who are interested in developing an Idea Garden for their end-user programming environments. Graduation date: 2013 2013-04-24T00:00:00Z http://hdl.handle.net/1957/38548 Improved stability in ACTFEL devices Khormaei, Iranpour The stability of ZnS:Mn AC thin film Electroluminescence (ACEFEL) devices as demonstrated by the brightness-voltage (BV) characteristics is discussed. Two procedures for improvement of the stability are demonstrated. The first method is the addition of a CaS buffer layer to one or both interfaces of the ZnS active phosphor layer. The second method for improving the stability involves a vacuum anneal followed by an oxygen exposure. The oxygen exposure is accomplished by heat treatment of the ZnS surface in air or an oxygen plasma prior to the deposition of the second insulator. A model for the observed instability is proposed in which accumulation of positive charge near the ZnS insulator interfaces gives rise to the observed increase in the BV threshold voltage with aging for the control sample. The positive interface charge is attributed to sulfur vacancies which are positively ionized donors. The improved device stability is attributed to a reduction in the sulfur vacancy concentration in the ZnS concomitant with the addition of a CaS buffer layer or oxygen exposure of the ZnS surface. Graduation date: 1990 1989-06-23T00:00:00Z