Theses (Electrical Engineering and Computer Science)

Design and FPGA implementation of digital transmission over severe ISI channels

Tue, 28 May 2013 00:00:00 GMT

Design and FPGA implementation of digital transmission over severe ISI channels Zhao, Yichen Inter-symbol interference is one of the major factors that make the realization of high-data-rate digital communications system complex. Current designs face two main challenges: how to efficiently utilize the available bandwidth and how to reduce the hardware complexity of the transmitter and receiver. Traditional solutions use a single-band architecture. When ISI is severe, it might require an equalizer to mitigate ISI, which usually results in a high complexity and power consumption. This thesis focuses on the analysis and FPGA implementation of a multiband communication architecture. This design ensures that the channel frequency response in each sub-band is approximately flat to avoid the need of an equalizer. Specifically, a four-band architecture is presented in detail, and this design is compared with the single-band approach. First, basic theories are provided for convenience of understanding the major development in this thesis in terms of simulation and FPGA implementation. Then the channel characteristics, such as the frequency and impulse responses, are analyzed for a four-band architecture. The single- and four-band architectures are introduced separately and optimized in detail. The simulation results of both architectures are verified through FPGA implementation in the Xilinx Virtex5 development board. Finally, BERs of the two architectures are compared from both simulation and FPGA implementation results. Graduation date: 2013

Design techniques for low-power multi-GS/s analog-to-digital converters

Mon, 10 Jun 2013 00:00:00 GMT

Design techniques for low-power multi-GS/s analog-to-digital converters Jiang, Tao Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off of the number of the channels and the sampling rate in each channel. Phase misalignment and channel mismatch must be considered too. Second, timing accuracy, especially dynamic jitter of sampling clock becomes a major concern at ultra-high frequency, and certain techniques must be taken to address it. Finally, to achieve low power consumption, Flash architecture is not suitable to serve as the sub-ADC, and a low-power sub-ADC that can work at relatively high speed need to be designed. A single channel, asynchronous successive approximation (SA) ADC with improved feedback delay has been fabricated in 40nm CMOS. Compared with a conventional SA structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SA-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator’s quantization delay, as the digital logic delay is eliminated. Measurement results of the 40nm-CMOS SA-ADC achieves peak SNDR of 32.9dB at 1GS/s and 30.5dB at 1.25GS/s, consuming 5.28mW and 6.08mW respectively, leading to FoM of 148fJ/conversion-step and 178fJ/conversion-step, in a core area less than 170µm by 85µm. Based on the previous work of sub-ADC, a 12-GS/s 5-b 50-mW ADC is designed in 40nm CMOS with 8 time-interleaved channels of Flash-SA hybrid structure each running at 1.5GS/s. A modified bootstrapped switch is used in the track-and-hold circuit, introducing a global clock signal to synchronize the sampling instants of each individual channel, therefore improve the phase alignment and reduce distortion. The global clock is provided by a CML buffer which is injected by off-chip low-noise sine-wave signal, so that the RMS dynamic jitter is low for better ENOB performance. Measurement results show that the 12GS/s ADC can achieve a SNDR of 25.8dB with the input signal frequency around DC and 22.8dB around 2GHz, consuming 32.1mW, leading to FoM of 237.3fJ/conversion-step, in a core area less than 800µm by 500µm. Graduation date: 2013

Flexible dual TCP/UDP streaming for H.264 HD video over WLANs

Thu, 30 May 2013 00:00:00 GMT

Flexible dual TCP/UDP streaming for H.264 HD video over WLANs Zhao, Jing High Definition video streaming over WLANs faces many challenges because video data requires not only data integrity but also frames have strict playout deadline. Traditional streaming methods that rely solely on either UDP or TCP have difficulties meeting both requirements because UDP incurs packet loss while TCP incurs delay. This thesis proposed a new streaming method called Flexible Dual-TCP/UDP Streaming Protocol (FDSP) that utilizes the benefit of both UDP and TCP. The FDSP takes advantage of the hierarchical structure of the H.264/AVC syntax and uses TCP to transmit important syntax elements of H.264/AVC video and UDP to transmit non-important elements. Moreover, if desired, FDSP is flexible enough to send any H.264 syntax element via TCP. The proposed FDSP is implemented and validated under different wireless network conditions. Both visual quality and delay results are compared against pure-UDP and pure-TCP streaming methods. Our results show that FDSP effectively achieves a balance between delay and visual quality, thus it has advantage over traditional pure-UDP and pure-TCP methods. Graduation date: 2013

Fast queuing policies via convex relaxation

Mon, 20 May 2013 00:00:00 GMT

Fast queuing policies via convex relaxation Nguyen-Huu, Duong Traditionally, networking protocol designs have placed much emphasis on point-to-point reliability and efficiency. With the recent rise of mobile and multimedia applications, other considerations such as power consumption and/or Quality of Service (QoS) are becoming increasingly important factors in designing network protocols. As such, we present a new flexible framework for designing robust network protocols under varying network conditions that attempts to integrates various given objectives while satisfying some pre-specified levels of Quality of Service. The proposed framework abstracts a network protocol as a queuing policy, and relies on the optimization methods of convex relaxation and the theory of mixing time for finding the fast queuing policies that drive the distribution of packets in a queue to a given target stationary distribution. It is argued that a target stationary distribution can be used to characterize various performance metrics of network flow. Thus, finding a fast queuing policy that produces a given target stationary distribution is vital in achieving some given objectives. In addition, we show how to augment the basic proposed framework in order to obtain a queuing policy that produces ε-approximation to the target distribution with even faster convergence time. This fast adaptation is especially useful for networking applications in fast-changing network conditions. Both theory and simulation results are presented to verify our framework. Graduation date: 2013