Abstract:
A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system operates with a supply voltage down to 250 mV. A
prototype has been fabricated in a 0.13μm CMOS process and includes a low voltage
LNA, quadrature oscillators, and quadrature mixers. It exhibits an order of magnitude
lower power consumption than the best previously published work. The system has a
measured gain of 42 dB, a noise figure of 8.6 dB, and an oscillator phase noise of -113.8 dBc/Hz at a 1 MHz offset while consuming a maximum of 580 μW of power and requiring no external components.
