Abstract:
The exponential rate of advances in modern communication devices in the last several
years have brought us higher levels of functionality and performance as well as
reductions in physical size and power consumption. To continue this rate of
advancement, next generation systems require wider bandwidth and higher resolution
ADCs. Additionally, in order for ADCs to be used in a wide range of applications,
reconfigurability and adaptability are critical features of future ADCs. Reconfigurable
ADC architectures allow consolidation of receivers for multiple communication
standards into one, providing size, power and functionality improvements over multiple
discrete ADCs. This thesis presents a high performance track-and-hold block and
reconfigurable high performance ADC for multi-functional communication
applications.
In the design of analog-to-digital converters (ADCs), the front-end track-and-hold or
sample-and-hold is often one of the most challenging parts of the design. Open-loop designs with high sample rates are reaching the limits of their linearity. Presented here
is a high-speed, high-resolution closed-loop track-and-hold in a 0.18um SiGe BiCMOS
technology. The architecture provides both high linearity and high speed, with 98.7dB
and 89.4dB SNDR at 50MS/s and 100MS/s, respectively.
As these specifications evolve to meet customer demands, new, high performance
ADCs are needed. To this end, an efficient parallel ΔΣ ADC architecture has been
designed that achieves high performance in digital processes, while also providing
additional architecture flexibility. This ADC, consisting of four parallel ΔΣ ADCs and
a single pipeline ADC provides high performance and reconfigurablity. This ADC is
suited to applications requiring not only wide-bandwidth, high resolution signal
conversion but an on-the-fly reconfigurable resolution and bandwidth.
