Ultra-low energy digital logic controller design for wireless sensor networks

Abstract

Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes. Transistor level simulations are used to evaluate the techniques and those demonstrating an energy reduction are used to implement a digital logic controller. The digital controller for the wireless sensor node, fabricated in a 0.18μm CMOS process, operates at 350mV while consuming 336fJ per clock cycle with a 250kbps data rate. Lab measurements show a 98% reduction in energy consumption compared to an implementation that utilizes standard design techniques, making it the lowest energy digital controller for wireless sensor nodes to date.