Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes

Graduate Thesis Or Dissertation

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Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/sj139490z

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Attribute Name	Values
Creator	Pham, Hui En
Abstract	Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to verify that the modeling approach used in simulation and the substrate noise model obtained using Silencer! is accurate to within 10%. The effects of a deep trench moat structure, bulk separation, and die perimeter ring were also tested as possible noise reduction methods. Strategies for simulation and measurement of substrate noise coupling in a 0.18¹m SOI process are also presented.
License	All rights reserved
Resource Type	Masters Thesis
Date Available	2009-05-12T16:14:31+00:00
Date Issued	2004-08-24
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Computer Engineering
Degree Grantor	Oregon State University
Commencement Year	2005
Advisor	Mayaram, Karti Fiez, Terri
Academic Affiliation	Electrical Engineering and Computer Science
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Substrate noise Systems on a chip -- Noise Silicon-on-insulator technology -- Noise
Rights Statement	In Copyright
Publisher	Oregon State University
Language	English [eng]
Replaces	http://hdl.handle.net/1957/11551

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