Abstract:
Strategies for simulation and measurement of substrate noise have been analyzed using various digital and analog circuits fabricated in the TSMC 0.35um heavily doped CMOS process. The measurements validate a substrate noise coupling macromodel that has been used to obtain the simulation results. The simulations and measurements also substantiate the effectiveness of various noise suppression techniques. Additionally, strategies for simulation and measurement have been extended and circuits have been designed for verification of these strategies in the IBM 7HP 0.18um lightly doped BiCMOS process.
