Abstract:
Modern day digital systems employ frequency
synthesizers to provide a common clock to the system.
They are undergoing large scale integration due to which, mitigation
of the effect of noise on power supply has become a major design consideration
in clocking circuits. Rapid scaling of CMOS technology mandates the
design of frequency synthesizers in a low supply voltage environment.
Maintaining the supply noise immunity of clocking circuits in low-voltage
processes is particularly challenging.
In this thesis, techniques to mitigate the effect of supply-noise
in frequency synthesizers are
explored. The ring-oscillator based frequency synthesizer
is an important part of many clocking circuits.
They are used in various digital communication systems and as a
building block in high speed signalling systems.
They suffer from high sensitivity to power supply noise thereby requiring
careful design considerations to improve its supply noise immunity.
In light of the above, an attempt has been made to
improve the immunity of the ring-oscillator based frequency synthesizer
to noise on the supply voltage. The effect of noise on
the supplies of other building blocks of a frequency synthesizer,
though not as pronounced as that of noise on the ring-oscillator supply,
is quite significant. Analysis of effect of power supply noise on
various building blocks of the frequency synthesizer are presented.
Also, techniques to effectively reduce the effect of power supply noise
on the performance of the frequency synthesizer are presented.
Measured results from proof-of-concept ICs are presented to illustrate the
effectiveness of the proposed techniques.
Clock and data recovery (CDR) circuits which utilize ring-oscillators are
also highly sensitive to power supply noise. Measurement of CDR jitter
tolerance without the use of expensive equipment is another challenge involved
in the design of CDRs. An on-chip jitter tolerance measurement technique is
presented wherein, a phase averaging dual loop CDR architecture is used
which comprises of a phase-locked loop (PLL) inside the CDR loop.
Previously proposed idea of using oversampling in this architecture has proven
to considerably
reduce power consumption in this CDR architecture. In this thesis, an
attempt has been made to further reduce the power consumption.
The PLL in this CDR architecture utilizes the proposed supply regulated PLL
architecture in order to minimize the bit-error rate (BER) of the CDR due to
power supply noise.
