Abstract:
The design of a switched capacitor successive approximation A/D converter
is discussed in this thesis. This design adopts a novel capacitance mismatch
error cancellation algorithm proposed in references [25, 27]. Detailed charge
domain analysis is given in this thesis, which results in an improvement of the
proposed algorithm by tracing the error charge free capacitors. The theoretical
work analyzing the inadequacy of normal predictive correlated double sampling
(CDS) technique to compensate operational amplifier non-idealities on high
precision switched capacitor successive approximation A/D converter is also
provided and verified by system level simulations. As a new compensation
technique, predictive correlated triple sampling (CTS) technique is introduced
and verified by simulations. This technique is used in the final design. Transistor
level full chip design is completed and fabricated through the work of this thesis.
