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Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization

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dc.contributor.advisor Allstot, David J.
dc.creator Gao, Hairong
dc.date.accessioned 2012-10-09T19:10:33Z
dc.date.available 2012-10-09T19:10:33Z
dc.date.copyright 1997-06-23
dc.date.issued 1997-06-23
dc.identifier.uri http://hdl.handle.net/1957/34282
dc.description Graduation date: 1998 en_US
dc.description.abstract Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm. A mixed-signal IC implementation has been chosen for the parallel MDFE. The differential current signals from the feedback equalizer are subtracted from the forward equalizer output at the summing node to cancel the non-causal ISI. A high-speed comparator with 6 bit resolution is used after the cancellation to detect the signal which contains no ISI. In this thesis, a description of the parallel MDFE structure and decision feedback equalization algorithm are presented. The design of a high-speed summing circuitry and a high-speed comparator are discussed. The same comparator design is used for the flash analog-to-digital converter (ADC) which generates error signals for adaptation.The circuits design and layout were carried out in an HP 1.2-μm n-well CMOS process. en_US
dc.language.iso en_US en_US
dc.subject.lcsh Feedback control systems -- Design and construction en_US
dc.subject.lcsh Computer arithmetic en_US
dc.subject.lcsh Parallel processing (Electronic computers) en_US
dc.subject.lcsh Analog-to-digital converters en_US
dc.title Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization en_US
dc.type Thesis/Dissertation en_US
dc.degree.name Master of Science (M.S.) in Electrical and Computer Engineering en_US
dc.degree.level Master's en_US
dc.degree.discipline Engineering en_US
dc.degree.grantor Oregon State University en_US
dc.contributor.committeemember Kiaei, Sayfe
dc.contributor.committeemember Weisshaar, Andreas
dc.contributor.committeemember Schultz, Robert J.
dc.description.digitization File scanned at 300 ppi (Monochrome) using ScandAll PRO 1.8.1 on a Fi-6670 in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR. en_US
dc.description.peerreview no en_us


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