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A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

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  • A reference-less highly digital half-rate clock and data recovery (CDR) circuit with improved tolerance to input duty cycle error is presented. Using a chain of frequency dividers, the proposed frequency detector produces a known sub-harmonic tone from the incoming random data. A digital frequency-locked loop uses the extracted tone, and drives the oscillator to any sub-rate of the input data frequency. The early/late outputs of a conventional half-rate bang-bang phase detector are used to determine the duty-cycle error in the incoming random data and adjust the oscillator clock phases to maximize receiver timing margins. Fabricated in 0.13 μm CMOS technology, the prototype digital CDR operates without any errors from 0.5 Gb/s to 2.5 Gb/s. At 2 Gb/s, the prototype consumes 6.1 mW power from a 1.2V supply. The proposed clock-phase calibration is capable of correcting up to ±20% of input data duty-cycle error.
  • This is the author's peer-reviewed final manuscript, as accepted by the publisher. The published article is copyrighted by IEEE-Institute of Electrical and Electronics Engineers and can be found at: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4.
  • Keywords: data duty cycle error, optimal sampling, clock phase calibration, power spectral density of random NRZ data, linear delay cell, Digital CDR, reference-less frequency acquisition
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  • Inti, R.; Yin, W.; Elshazly, A.; Sasidhar, N.; Hanumolu, P.K.; , "A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance," IEEE Journal of Solid-State Circuits, vol.46, no.12, pp.3150-3162, Dec. 2011 doi: 10.1109/JSSC.2011.2168872
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  • 46
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  • 12
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