A new RISC architecture for high speed data acquisition

Graduate Thesis Or Dissertation

Public Deposited

Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/6682x631m

Descriptions

Attribute Name	Values
Creator	Gribble, Donald L.
Abstract	This thesis describes the design of a RISC architecture for high speed data acquisition. The structure of existing data acquisition systems is first examined. An instruction set is created to allow the data acquisition system to serve a wide variety of applications. The architecture is designed to allow the execution of an instruction each clock cycle. The utility of the RISC system is illustrated by implementing several representative applications. Performance of the system is analyzed and future enhancements discussed.
Resource Type	Masters Thesis
Date Available	2013-02-19T18:30:04+00:00
Date Issued	1991-11-12
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Computer Engineering
Degree Grantor	Oregon State University
Commencement Year	1992
Advisor	Herzog, James H.
Academic Affiliation	Electrical and Computer Engineering
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Reduced instruction set computers Computer architecture Automatic data collection systems
Rights Statement	Copyright Not Evaluated
Publisher	Oregon State University
Peer Reviewed	No
Language	English [eng]
Digitization Specifications	File scanned at 300 ppi (Monochrome) using ScandAll PRO 1.8.1 on a Fi-6770A in PDF format. CVista PdfCompressor 5.0 was used for pdf compression and textual OCR.
Replaces	http://hdl.handle.net/1957/37001

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