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Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End

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  • A noise-shaped pipelined ADC is presented in this paper. A minimal complexity ΔΣ modulator in the first two sub-ADCs and residue feedback in the latter stages lead to high-order noise shaping. This also leads to reduced sensitivity to analog imperfections in the front-end stage. Implemented in 0.18μ m CMOS, the ADC achieves 12 ENOB with 64 MHz clock at 6X OSR while using only a 9-bit linear front-end multiplying-DAC (MDAC). The delta-sigma sub-ADCs dissipate 400μ W extra power (out of 13.9mW total power) while significantly enhancing the the overall ADC linearity.
  • This is an author's peer-reviewed final manuscript, as accepted by the publisher. The published article is copyrighted by IEEE-Institute of Electrical and Electronics Engineers and can be found at: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4. (c) 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
  • Keywords: pipelined analog-to-digital converters, switched-capacitor circuits, loop filter, feedback DAC., noise shaping, ΔΣ modulation, oversampling converters
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  • Rajaee, O.; Un-Ku Moon, "Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End," Solid-State Circuits, IEEE Journal of, vol.48, no.2, pp.502,515, Feb. 2013 doi: 10.1109/JSSC.2012.2227605
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  • 48
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  • 2
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  • This work was supported in part by SRC and CDADIC.
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