Model and design of cmos phase-locked loop

Graduate Thesis Or Dissertation

Public Deposited

Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1z40kx083

Descriptions

Attribute Name	Values
Creator	Shum, Daniel K.
Abstract	This thesis will examine the model and design technique of a self-contained analog CMOS Phase-Locked Loop. This system has an adaptable filter and demodulator for an oscillating frequency of up to 1000 KHz and it is programmable by means of an external resistor and capacitor. The first topic to be presented will be the nonlinear feedback system concept and terminology, then the mathematical analysis for the phase comparator, low-pass filter, voltage-controlled oscillator and capture and lock range is developed. Finally, the circuit parameters, description, simulation and layout will be presented.
Resource Type	Masters Thesis
Date Available	2013-06-04T19:09:20+00:00
Date Issued	1989-06-29
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Computer Engineering
Degree Grantor	Oregon State University
Commencement Year	1990
Advisor	Allstot, David J.
Academic Affiliation	Electrical and Computer Engineering
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Linear integrated circuits -- Design and construction Phase-locked loops
Rights Statement	Copyright Not Evaluated
Publisher	Oregon State University
Peer Reviewed	No
Language	English [eng]
Digitization Specifications	File scanned at 300 ppi (Monochrome, 8-bit Grayscale) using ScandAll PRO 1.8.1 on a Fi-6770A in PDF format. CVista PdfCompressor 5.0 was used for pdf compression and textual OCR.
Replaces	http://hdl.handle.net/1957/38954

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