IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology

Graduate Thesis Or Dissertation

Public Deposited

Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/g445ch855

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Attribute Name	Values
Creator	Rajanala, Arunkumar V.
Abstract	Typically, a Floating Point processor will be attached to a general-purpose digital computer to extend and enhance its numeric processing capabilities. In this thesis a multiple instruction, multiple data machine for the addition, subtraction, multiplication and division of floating point numbers is presented. The algorithms used have been partitioned to optimise utilisation of the parallel structure. The processor was implemented and simulated on the Silicon Compiler, a commercial computer-aided design tool. The resulting chip is ready for fabrication and is 323*295 mils in size and can operate with a 5.8 MHz clock for a two micron CMOS process.
Resource Type	Masters Thesis
Date Available	2013-06-28T23:38:47+00:00
Date Issued	1988-07-07
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Computer Engineering
Degree Grantor	Oregon State University
Commencement Year	1989
Advisor	Murray, John
Academic Affiliation	Electrical and Computer Engineering
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Microprocessors Floating-point arithmetic
Rights Statement	Copyright Not Evaluated
Publisher	Oregon State University
Peer Reviewed	No
Language	English [eng]
Digitization Specifications	File scanned at 300 ppi (Monochrome) using ScandAll PRO 1.8.1 on a Fi-6770A in PDF format. CVista PdfCompressor 5.0 was used for pdf compression and textual OCR.
Replaces	http://hdl.handle.net/1957/39940

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