A fully integrated CMOS latched comparator is presented for use as a wake-up circuit that is attached to an RF energy harvester in a battery free wireless sensor network. The system consumes less than 36nA static current ...

"Fifty years after the pioneering work of McCulloch and Pitts, the study of neural nets is alive and active. In this paper, I have discussed some of the work that is of current interest to me and my co-workers. I would, ...

The classical store-and-forward routing has and will continue to be the most important routing architecture in many modern packet-switched communication networks. In a packet-switched network, data is sent in the form of ...

Since its introduction in the early 1990s, the quick growth of the World Wide Web (WWW) traffic raises the question of whether past Local Area Network (LAN) packet traces still reflect the current situation or whether ...

The main focus of this work is on the problem of existence of nonlinear optimal controllers realizable by artificial neural networks. Theoretical justification, currently available for control applications of neural ne ...

A new and improved stabilizer was developed for the variable speed generation (VSG) system. The VSG system exhibits periodic oscillations which sometimes leads to a loss of synchronism. After careful study, a simple bu ...

This thesis presents new, compact configurations for RF/microwave bandstop and lowpass filters for embedded passive applications. A simple design methodology is presented for designing the folded-transmission line filter ...

The recent demand for wireless transceivers has created a flurry of research into nontraditional receiver architectures. The homodyne receiver, because of its high degree of integration, low complexity and low power co ...

We describe novel methods for obtaining fast software implementations of the arithmetic operations in the finite field GF(p) and GF(p[superscript k]). In GF(p) we realize an extensive speedup in modular addition and su ...

This thesis describes the design of a RISC architecture for high speed data acquisition. The structure of existing data acquisition systems is first examined. An instruction set is created to allow the data acquisitio ...