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Browsing Theses (Electrical Engineering and Computer Science) by Author

Browsing Theses (Electrical Engineering and Computer Science) by Author "Temes, Gabor"

Now showing items 1-20 of 39

Adaptive correction techniques for delta-sigma A/D converters

Abdennadher, Salem (1992-05-28)

Oversampling analog-to-digital and digital-to-analog converters are gaining more popularity in many signal processing applications. Delta-sigma modulators are used in practical applications of oversampling systems becau ...
Analysis and modeling of single-ended and differential spiral inductors in silicon-based RFICs

Watson, Adam C. (2003-12-02)

A new comprehensive wide-band compact modeling methodology for single-ended spiral inductors and differential spiral inductors is presented. The new modeling methodology creates an equivalent circuit model consisting o ...
Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters

Maghari, Nima (2010-10-12)

Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to noise and distortion ratio (SNDR) and most important of al ...
Architecture design of multiplexed incremental analog-to-digital converters

Zhang, Zhiqing (2007-11-21)

Analog-to-Digital Data Converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental data converters (IDCs) provide ...
Broadband modeling of on-chip transformers for silicon RFICs

Rapolu, Kavitha (2008-10-30)

Magnetically coupled passive transformers are increasingly integrated on-chip for various analog and radio frequency (RF) applications including direct current (DC) isolation, impedance transformation/matching, and con ...
A comparative study between sinusoidal and squarewave clocking for alleviating the jitter limitation in multi-gigaHertz ADCs

Kesharwani, Divya (2010-03-11)

Abstract: Various applications like wireless UWB communication, fast data acquisition systems and digital storage oscilloscopes needs ADCs with instantaneous input signal bandwidth from 0.1-40 GigaHertz range with 6-10 ...
A comparative study of lowpass continuous-time delta-sigma modulators with pulse-shaped DACs

Fang, Jie (2005-10-24)

Recently, continuous-time ΔΣ modulators are appearing increasingly often in both the literature and the marketplace due to their features of inherent antialiasing and relaxed requirements for opamp and so on. However, se ...
Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps

Gregoire, B. Robert (2008-12-17)

This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution of this thesis is a new switched-capacitor method ...
Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate

Jiang, Ruoxin (2001-07-30)

In this dissertation, a new Δ∑ A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure, which can realize a high maximum out-of-band quantiz ...
Design of a low jitter digital PLL with low input frequency

Jung, Seokmin (2012-06-05)

Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as ...
Design of low power 2.4GHz CMOS LC balanced oscillators with low phase noise and large tuning range

Seshan, Nilakantan (2002-01-25)

The design of two 2.4GHz CMOS LC balanced oscillators in the 0.25μm National BiCMOS process for Bluetooth specifications is presented. These oscillators achieve low phase noise with low power consumption. At a frequenc ...
Design techniques for clocking high performance signaling systems

Hanumolu, Pavan Kumar (2006-11-28)

Scaling of CMOS technology has progressed relentlessly for the past several decades. In order for this unprecedented scaling to benefit the performance of large digital systems, the communication bandwidth between inte ...
Design techniques for high-performance digital PLLs and CDRs

Yin, Wenjing (2010-12-01)

Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as leakage, poor analog transistor beha ...
Design techniques for low-voltage and low-power analog-to-digital converters

Ahn, Gil Cho (2005-10-18)

With the ever-increasing demand for portable devices used in applications such as wireless communication, mobile computing, consumer electronics, etc., the scaling of the CMOS process to deep submicron dimensions becom ...
Design techniques for PVT tolerant phase-locked loops

Wu, Ting (2007-01-29)

The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing ...
A digital multiplying delay locked loop for high frequency clock generation

Uttarwar, Tushar (2011-11-21)

As Moore’s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough chal ...
A DSP controlled resonant active filter for current harmonic mitigation in three-phase power systems

Ünsal, Abdurrahman (2000-12-01)

Power quality has become an important concern to both electric utilities and end users due to the increased use of non-linear loads in modem power systems over the past decade. Nonlinear loads inject harmonics into the ...
Dual referencing guidelines to minimize power delivery noise coupling

Mark, Shannon (2011-06-10)

Dual referencing has been garnering a lot of attention in the power integrity community, specifically in the voltage mode driver application because it shows a lower overall power delivery noise (PDN) compared to other s ...
A dual-path 2-0 MASH ADC with dual digital error correction

Zhang, Zhenyong (2007-01-08)

This dissertation presents a dual-path 2-0 MASH (Multi-stAge-noise -SHaping) ADC with two verified digital corrections of DAC mismatch error and quantization noise leakage. By using these two techniques, the requirements ...
Enhanced-accuracy oversampled data converters

Ceballos, Jose Luis (2005-10-24)

Digital-to-analog converters (DACs) suffer from static and dynamic nonlinearity problems, which degrade their accuracy and performance. Mismatch errors in the analog components restrict the maximum achievable linearity. ...