Substrate noise coupling in ring oscillator-based phase locked loops

Abstract

In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35 μm CMOS process. Since the model is physical, it can be used to predict substrate noise coupling without the need for extensive computer simulations using three-dimensional finite difference or Green's function solvers. This is followed by an evaluation of the effect of substrate noise in a PLL. A PLL test chip fabricated in a 0.13 μm CMOS process has been characterized over a wide range of substrate noise frequencies. The measured results combined with extensive simulations provide insight into the mechanisms for noise coupling in a PLL. Based on an understanding of the noise coupling, guidelines for minimizing the impact of substrate noise are presented.