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Filtering by: Subject Phase-locked loops -- Design and construction -- Evaluation Remove constraint Subject: Phase-locked loops -- Design and construction -- Evaluation Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science

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  • Characterization of a digital phase locked loop and a stochastic time to digital converter

    Creator:
    Geissenhainer, Erik D.
    Abstract:
    A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited...
    Resource Type:
    Masters Thesis
    Full Text:
    presented on July 21, 2006. Title: Characterization of a Digital Phase Locked Loop and a Stochastic

  • Design of a low jitter digital PLL with low input frequency

    Creator:
    Jung, Seokmin
    Abstract:
    Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog...
    Resource Type:
    Masters Thesis
    Full Text:
    of such a support circuit is the phase-locked loop (PLL). PLL circuits are traditionally used in

  • Design techniques for clocking high performance signaling systems

    Creator:
    Hanumolu, Pavan Kumar
    Abstract:
    Scaling of CMOS technology has progressed relentlessly for the past several decades. In order for this unprecedented scaling to benefit the performance of large digital systems, the communication bandwidth between integrated circuits (ICs) must scale accordingly. However, interconnect technology does not scale as aggressively, making communication between chips the major...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.16 Phase-locked loop that provides 8-phases. . . . . . . . . . . . . . . . . . . . . . . . 40

  • Development test suite for FPGA TekBot learning platform

    Creator:
    Lai, Gerald
    Abstract:
    As the Tekbots program expands into senior and graduate level classes at Oregon State University, so does the need arise for more complex learning platforms. These complex hardware platforms cannot be adequately tested in a manufacturing environment as we have done previously. Also, due to their complexity, these platforms require...
    Resource Type:
    Masters Thesis
    Full Text:
    established design flow processes often found in the engineering industry. Crippled simulators and stripped