Search Constraints

Start Over
Filtering by: Committee Member Tenca, Alexandre F. Remove constraint Committee Member: Tenca, Alexandre F. Advisor Lee, Il Beom Remove constraint Advisor: Lee, Il Beom

Search Results

  • Multithreaded virtual processor on DSM

    Creator:
    An, Ho Seok
    Abstract:
    Modern superscalar processors exploit instruction-level parallelism (ILP) by issuing multiple instructions in a single cycle because of increasing demand for higher performance in computing. However, stalls due to cache misses severely degrade the performance by disturbing the exploitation of ILP. Multiprocessors also greatly exacerbate the memory latency problem. In SMPs,...
    Resource Type:
    Masters Thesis
    Full Text:
    thanks to the committee members, Prof. Alexandre F. Tenca, Prof. Kyoung Rok Cho, and Prof. Robert M

  • Eager data transfer mechanism for user-level network protocol

    Creator:
    Won, Chulho
    Abstract:
    This dissertation investigates the use of a hardware mechanism called Eager Data Transfer (EDT) for achieving the reduction of communication latency for user-level network protocol. To reach the goal, the dissertation addresses the following research issues. First, the development of a communication system performance evaluation tool called Linux/SimOS is presented....
    Resource Type:
    Dissertation
    Full Text:
    F. Tenca, Dr. Molly Shor, Dr. Huaping Liu, and Dr. Harold Parks for providing valuable time and