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Filtering by: Advisor Mayaram, Kartikeya Decade 2000-2009 File Format application/pdf

A substrate noise coupling model for lightly doped CMOS processes

Simulation and modeling of substrate noise generation from synchronous and asynchronou...

Comparison and impact of substrate noise due to clocked and clockless circuitry

Design techniques for PVT tolerant phase-locked loops

Digital phase-locked loops for multi-GHz clock generation

Computationally efficient substrate noise coupling estimation in lightly doped silicon...

Ground tap placement and sizing to minimize substrate noise coupling in RF LNAs

Comparison of time-domain and frequency-domain phase noise analyses

An efficient and accurate method of estimating substrate noise coupling in heavily dop...

A stochastic time-to-digital converter for digital phase-locked loops

Oscillators and phase locked loops for space radiation environments

Design techniques for radiation hardened-phase locked loops

A test fixture and deembedding procedure for high-frequency substrate characterization