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Filtering by: Creator Peterson, K. J. Remove constraint Creator: Peterson, K. J. Advisor Moon, Un Ku Remove constraint Advisor: Moon, Un Ku

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  • A multi-bit hybrid DSM over full-scale range without feedback DEM

    Creator:
    Kwon, Sunwoo, 1974-
    Abstract:
    Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
    Resource Type:
    Dissertation
    Full Text:
    -domain when zk = 1 1 z−zk ro s−sk × 1 z1−αk −z1−βk ro s r0 = sk r0 = 1β−α 1 (z−zk)2 r1s+r0 (s−sk)2

  • Power-efficient two-step pipelined analog-to-digital conversion

    Creator:
    Lee, Ho-Young
    Abstract:
    Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which...
    Resource Type:
    Dissertation
    Full Text:
    Page 5.8. Power consumption ratio  vs. (a) logic delay td and (b) scaling factor k

  • Low power high resolution data converter in digital CMOS technology

    Creator:
    Zheng, Zhiliang
    Abstract:
    The advance of digital IC technology has been very fast, as shown by rapid development of DSP, digital communication and digital VLSI. Within electronic signal processing, analog-to-digital conversion is a key function, which converts the analog signal into digital form for further processing. Recently, low-voltage and low-power have become also...
    Resource Type:
    Masters Thesis
    Full Text:
    thanks to Prof. Robert J. Schultz of Civil, Construction, & Environmental Engineering Department for

  • A Wide Modulation Range and PVT-Tolerant Spread-Spectrum Modulation Clock Generator

    Creator:
    Sun, Hyuk
    Abstract:
    This dissertation presents a phase domain in-loop-bandwidth spread-spectrum clock generation technique. In this proposed technique, a charge-based discrete-time loop filter is proposed to enable the phase domain in-loop-bandwidth spread-spectrum modulation without a delta-sigma modulator or time-to-digital converter. The in-loop-bandwidth modulation technique maximizes the loop bandwidth to improve phase noise suppression...
    Resource Type:
    Dissertation
    Full Text:
    modulation. The output of the clock (VOUT(t)) is written as: OUT OUT n OUT SSC_ rate n V (t) A J ( ) cos

  • A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs

    Creator:
    Wang, Xuesheng
    Abstract:
    This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of the DAC error is indicated through a simple model for unit-element based DACs. The impact of the DAC error on the performance of ADC is...
    Resource Type:
    Dissertation
    Full Text:
    2.1 FS = v(k) 11 I u(k) 'U') Li9LLsJ!J q(k) t VLSB/2RNNNI -VLsB/2 Figure 2-2 Quantization noise

  • Comparison of time-domain and frequency-domain phase noise analyses

    Creator:
    Vytyaz, Igor
    Abstract:
    This thesis presents a comparison of time-domain and frequency-domain algorithms for phase noise calculation in oscillators. Floquet theory provides the mathematical foundation for these calculations and the numerical methods employ perturbation projection vectors (PPVs). The PPVs are an estimate of an oscillator's sensitivity to noise. The in-house circuit simulator SPICE3...
    Resource Type:
    Masters Thesis
    Full Text:
    ] , i, j = 1, . . . , n (2.29) where Jij is a K × K matrix, and K is the number of Fourier coefficients

  • Digital implementation of a mismatch-shaping successive-approximation ADC

    Creator:
    Coe, Matthew T.
    Abstract:
    Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order Δ∑ loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis...
    Resource Type:
    Masters Thesis
    Full Text:
    a first-order approximation) by the equation Error p(k)2[t(k) t(j)] (3.2) where t(k) = ±1 denotes

  • Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters

    Creator:
    Guerber, Jon
    Abstract:
    In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and...
    Resource Type:
    Dissertation
    Full Text:
    recognition then they get. Mr. Gary Peterson taught me the value of self-learning, went out of his way to

  • Design of high-performance pipeline analog-to-digital converters in low-voltage processes

    Creator:
    Myers, Charles Grant
    Abstract:
    Pipeline analog-to-digital converters (ADCs) have long been used in high-speed systems for power-efficient data conversion. Broadband communication and video processing systems are placing high demands on converter accuracy and speed (above 14 bits and in the multiple-MHz range). The increasing converter requirements coupled with lower supply voltages in modern processes...
    Resource Type:
    Masters Thesis

  • A 10 bit algorithmic A/D converter for a biosensor

    Creator:
    Rengachari, Thirumalai
    Abstract:
    This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter...
    Resource Type:
    Masters Thesis
    Full Text:
    _____________ Qj [ j AVhias 1**-------.,, ' r. Vth' I I I Detection Mode -. K - - - Calibration Mode Cain