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  • Low noise clocking for high speed serial links

    Creator:
    Brownlee, Merrick
    Abstract:
    As the functionality of digital chips continues to increase dramatically, chip- to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has be- come an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are...
    Resource Type:
    Dissertation
    Full Text:
    on eye opening 11 2.7 Eye diagram before and after receive jitter 12 2.8 (a) The effect of

  • A 1V 40mA Fast Transient Capless LDO with 7uA Quiescent Current in 180nm CMOS using Ring Amplifier with Adaptive Damping

    Creator:
    Xiao, Bohui
    Abstract:
    Ring amplification has emerged as an efficient technique to drive large capacitive loads in switched capacitor circuits. We propose circuit techniques to demonstrate the first application of a ring amplifier in a non-capacitive feedback system of a LDO. These techniques enable a simple cap-less LDO structure in 180nm CMOS that...
    Resource Type:
    Masters Thesis
    Full Text:
    Regulator……..….10 3. RING AMPLIFIER IN LDO..…………………………………………………….11 3.1. Design Procedure

  • 20-stage pipelined ADC with radix-based calibration

    Creator:
    Yun, Chong Kyu
    Abstract:
    A radix-based calibration technique was previously proposed with a two-stage algorithmic analog-to-digital converter (ADC). The objective of this work is to verify the capability of radix-based calibration for a true multi-stage ADC. In order to prove the idea, a single bit-per-stage, 20-stage pipelined ADC is designed in a 0.35-μm CMOS...
    Resource Type:
    Masters Thesis
    Full Text:
    , 3.3-V A/D Converter [11] ..... 11 3.4. A 12-b Digital-Background-Calibrated Algorithmic ADC [12

  • A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications

    Creator:
    Xiao, Ying
    Abstract:
    A novel switched-R-MOSFET-C input branch is proposed for low-voltage and high-linearity applications. The tunability is achieved by varying the clock duty cycle using an automatic tuning circuit. This tuning method does not involve a change in gate voltage, and is therefore particularly suitable for low-voltage applications. The advantages of the...
    Resource Type:
    Masters Thesis
    Full Text:
    ................................................................................... 11 2.1 Proposed Structure

  • Noise optimization for low-voltage CMOS audio preamplifier systems

    Creator:
    Brown, Matthew Eugene
    Abstract:
    There is a large and growing market for portable consumer audio products with very small size. As the size of these products is reduced, the area occupied by batteries becomes significant and hence limits the number of batteries to one. In order to build such small products, high levels of...
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 Device Operating Regions

  • A stochastic time-to-digital converter for digital phase-locked loops

    Creator:
    Ok, Kerem
    Abstract:
    Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...
    Resource Type:
    Masters Thesis
    Full Text:
    .............................................................................11 3.2. Simulink Model of the Stochastic TDC

  • High-performance delta-sigma analog-to-digital converters

    Creator:
    da Silva, Jose Barreiro
    Abstract:
    Multi-stage delta-sigma (ΔΣ) architectures, commonly known as MASH, are the preferred choice for analog-to-digital converters (ADCs) used in broadband communication applications, where high-resolution (above 14 bits) and high-bandwidth (several MHz) performances are required. Current state-of-the-art designs are capable of as much as 5-MS/s output data rates with 90-dB SNR. However,...
    Resource Type:
    Dissertation
    Full Text:
    its quantization error ................................ 11 2.6 Quantizer DC transfer curve and

  • Digital phase-locked loops for multi-GHz clock generation

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...
    Resource Type:
    Dissertation
    Full Text:
    model for a second-order CPPLL. . . . . . . . . . . . . . . . . . . . . . 11 2.5 Transform from an

  • Low power design techniques for analog-to-digital converters in submicron CMOS

    Creator:
    Musah, Tawfiq
    Abstract:
    Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical in the development of portable electronic devices with small feature size and long battery life. However, the design of analog and mixed-signal building blocks, especially...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Pipelined ADC

  • Automated synthesis of analog to digital conversion

    Creator:
    Weaver, Skyler
    Abstract:
    This thesis describes circuit architectures and techniques that facilitate the automatic synthesis and fabrication of analog-to-digital converters (ADCs). Since automated synthesis already exists for digital circuits and is part of the digital circuit design flow, this work demonstrates the feasibility of ADC synthesis with little or no modification to presently...
    Resource Type:
    Dissertation
    Full Text:
    ) Verilog module ‘comparator’ which implements a NAND3 based comparator (lines 6-11). b) Gate-level