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Filtering by: Creator Li, Xu Remove constraint Creator: Li, Xu Contributor advisor sim Mayaram, Kartikeya Remove constraint Contributor advisor sim: Mayaram, Kartikeya

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  • Contributions to substrate noise due to supply coupling and pin parasitics

    Creator:
    Adluri, Sirisha
    Abstract:
    This thesis presents the contributions to substrate noise due to supply coupling and the effect of pin parasitics on the substrate noise generated by digital circuits. Various sources of substrate noise and their effect on analog circuits sharing the same substrate are discussed. A simulation approach to isolate the various...
    Resource Type:
    Masters Thesis
    Full Text:
    confidence to continue in the field of Analog Circuits. I would like to thank Dr. Chengang Xu and Dr. Dean

  • Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

    Creator:
    Hsu, Shu-ching
    Abstract:
    This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
    Resource Type:
    Masters Thesis
    Full Text:
    Xu and Dr. Keith Levien for being my committee members. I would like to thank Dr. Chenggang Xu again

  • Substrate coupling macromodel for lightly doped CMOS processes

    Creator:
    Koteeswaran, Mohanalakshmi
    Abstract:
    A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of...
    Resource Type:
    Masters Thesis
    Full Text:
    thank Cheng-gang Xu for his help with his software EPIC and Jose Silva for all the time he spent

  • A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits

    Creator:
    Ayers, James S.
    Abstract:
    An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
    Resource Type:
    Masters Thesis
    Full Text:
    Arunachalam, Kingsuk Brahma, Husni Habal, Martin Held, Paul Hutchinson, Steven Law, Triet Le, Zhimin Li

  • A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

    Creator:
    Held, Martin A.
    Abstract:
    A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate...
    Resource Type:
    Masters Thesis
    Full Text:
    , Sirisha Adluri, Brian Owens, Chengang Xu, Chee Boon (Steven) Law, Patrick Birrer, Matt MacClary, SasiKu

  • Accurate and efficient simulation of synchronous digital switching noise in system on a chip

    Creator:
    Habal, Husni
    Abstract:
    A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
    Resource Type:
    Masters Thesis
    Full Text:
    greatly thankful to Shu-Ching Hsu, Patrick Birrer, Chenggang Xu, Brian Owens, and Sirisha Adluri for

  • Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

    Creator:
    Sharma, Ajit
    Abstract:
    This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
    Resource Type:
    Masters Thesis
    Full Text:
    have worked with them. I would also like to acknowledge Dr. Chenggang Xu and Dr. Lewis Semprini, for

  • Coupled circuit and device simulations for design of RF MEMS VCOs

    Creator:
    Behera, Manas
    Abstract:
    A new coupled circuit and electrostatic/mechanical simulator (COSMO) for the design of RF MEMS VCOs is presented in this thesis. The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating...
    Resource Type:
    Masters Thesis
    Full Text:
    my research work. I would also like to acknowledge Dr. Chenggang Xu and Yutao Hu, who took the

  • Prediction of phase noise and jitter in ring oscillators

    Creator:
    Barton, Nathen
    Abstract:
    This thesis presents distinctly different methods of accurately predicting phase noise and absolute jitter in ring oscillators. The phase noise prediction methods are the commercially available SpectreRF and isf_tool, a simulator developed in this work from the Hajimiri and Lee theory of phase noise. Absolute jitter due to deterministic supply...
    Resource Type:
    Masters Thesis

  • Analysis and design of CMOS RF LNAs with ESD protection

    Creator:
    Chandrasekhar, Vinay
    Abstract:
    An analysis that accounts for the effect of standard electrostatic discharge (ESD) structures on critical LNA specifications of noise figure, input matching and gain is presented. It is shown that the ESD structures degrade LNA performance particularly for higher frequency applications. Two LNAs, one with ESD protection and one without,...
    Resource Type:
    Masters Thesis
    Full Text:
    , Ruoxin Jiang, Raghuram Jon- nalagedda, Mohanalakshmi Koteeswaran, Zhimin Li, Oleg Mikulchenko, Manu