Search Constraints

Start Over
Filtering by: Alternative title ssim PacifiCorp Power-line right-of-way #2 Remove constraint Alternative title ssim: PacifiCorp Power-line right-of-way #2 Contributor advisor sim Moon, Un-Ku Remove constraint Contributor advisor sim: Moon, Un-Ku

Search Results

  • Power-efficient two-step pipelined analog-to-digital conversion

    Creator:
    Lee, Ho-Young
    Abstract:
    Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which...
    Resource Type:
    Dissertation
    Full Text:
    architecture, which is generally known as one of the most power-consuming analog-to-digital converters

  • Low power design techniques for high speed pipelined ADCs

    Creator:
    Lingam, Naga Sasidhar
    Abstract:
    Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get...
    Resource Type:
    Dissertation
    Full Text:
    argued that scaling might increase the power [1]. Performance of pipeline ADC which is 2 popularly

  • Low power high resolution data converter in digital CMOS technology

    Creator:
    Zheng, Zhiliang
    Abstract:
    The advance of digital IC technology has been very fast, as shown by rapid development of DSP, digital communication and digital VLSI. Within electronic signal processing, analog-to-digital conversion is a key function, which converts the analog signal into digital form for further processing. Recently, low-voltage and low-power have become also...
    Resource Type:
    Masters Thesis
    Full Text:
    design of low-power high- performance A/D converters in CMOS technology, and the non-ideal switched

  • Design techniques for low-voltage and low-power analog-to-digital converters

    Creator:
    Ahn, Gil Cho
    Abstract:
    With the ever-increasing demand for portable devices used in applications such as wireless communication, mobile computing, consumer electronics, etc., the scaling of the CMOS process to deep submicron dimensions becomes more important to achieve low-cost, low-power and high-performance digital systems. However, this downscaling also requires similar shrinking of the supply...
    Resource Type:
    Dissertation
    Full Text:
    power of the quantization error can be given by σE 2 = ∆2 12 , (4.2) and the maximum SNR of N-bit

  • Low power design techniques for analog-to-digital converters in submicron CMOS

    Creator:
    Musah, Tawfiq
    Abstract:
    Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical in the development of portable electronic devices with small feature size and long battery life. However, the design of analog and mixed-signal building blocks, especially...
    Resource Type:
    Dissertation
    Full Text:
    power- and area-efficient way of increasing the resolution of flash ADC, is to break the conversion

  • Low-power design techniques for low-voltage analog-to-digital converters

    Creator:
    Kim, Min Gyu
    Abstract:
    The demand for portable electronic systems and the continued down-scaling of device dimensions resulted in rapid improvement in the performance of integrated systems. Several low-voltage design techniques have been proposed to operate analog circuits with sub-1V supply. However, these techniques require higher power consumption to achieve large dynamic range while...
    Resource Type:
    Dissertation
    Full Text:
    , the quantization noise power can be expressed as the mean square of eQ: e2Q = ∆2 12 . (3.2) If the

  • Power-Efficient Design Techniques and Architectures for Scalable Submicron Analog Circuits

    Creator:
    Xu, Yang
    Abstract:
    As the CMOS process scales down to submicron, digital circuit performance improves, while reduced supply voltage and lower transistor intrinsic gain make it difficult to implement analog circuits in a power efficient manner. Therefore, it has become advantageous to shift more analog signal processing functions conventionally realized in voltage (analog)...
    Resource Type:
    Dissertation
    Full Text:
    ] accounting 2 for 34%−52% of the total power dissipation. What’s more, as the CMOS process scales

  • Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters

    Creator:
    Sharma, Vivek
    Abstract:
    This thesis proposes a novel technique for the design of pipelined and cyclic ADCs utilizing generalized radix gain stages. Several models have been proposed for the optimization of high performance pipelined ADCs by various researchers. This work builds upon them, using a simple but accurate model to estimate the optimal...
    Resource Type:
    Masters Thesis
    Full Text:
    The purpose of this research was to find a way to design a power-optimized pipelined ADC. As part of

  • Power efficient analog-to-digital converters using both voltage and time domain information

    Creator:
    Oh, Taehwan
    Abstract:
    As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain...
    Resource Type:
    Dissertation
    Full Text:
    prototype ADC implemented in a 0.13µm CMOS demonstrate peak SNDR of 69.3dB (11.2b ENOB) at 6.38mW power

  • Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps

    Creator:
    Gregoire, B. Robert
    Abstract:
    This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution of this thesis is a new switched-capacitor method named correlated level shifting (CLS). CLS enables true rail-to-rail operation by storing an estimate of the desired...
    Resource Type:
    Dissertation
    Full Text:
    power-efficient way to increase DC gain, but, as the figure illustrates, it needs 600mV of headroom