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Filtering by: Contributor advisor sim Murray, John M. Remove constraint Contributor advisor sim: Murray, John M.

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The architecture and design of a parallel sorting engine

Creator:

Bate, John G.

Abstract:

Sorting is typically a compute intensive operation used in many areas of industry. With improved technology, both in the VLSI and CAE areas, we can afford to develop hardware based database computers to move the work load off the main computer. In this thesis the architecture of a VLSI parallel...

Resource Type:

Masters Thesis
Analysis and synthesis of neural networks

Creator:

Skelton, Jeanette K.

Abstract:

The brain has long attracted the interest of researchers. Some tasks, such as pattern recognition and optimization, have proven to be exceptionally difficult for conventional computing systems to perform, but are executed by the brain almost effortlessly. Due to the large number of neurons and interconnections, it has proven impossible...

Resource Type:

Masters Thesis
The design of a single chip logic state analyzer

Creator:

Hung, Shih-chuan

Abstract:

This thesis describes the design of a single-chip logic analyzer. The utility of such a chip in measuring and recording digital system parameters is illustrated. Possibilities for future applications of this chip in performance monitoring of computer systems are discussed.

Resource Type:

Masters Thesis
The analysis and synthesis of a parallel sorting engine

Creator:

Ahn, Byoungchul

Abstract:

This thesis is concerned with the development of a unique parallel sort-merge system suitable for implementation in VLSI. Two new sorting subsystems, a high performance VLSI sorter and a four-way merger, were also realized during the development process. In addition, the analysis of several existing parallel sorting architectures and algorithms...

Resource Type:

Dissertation
An implementation of the Department of Defense's transmission control protocol internet protocol (TCP/IP) for the Microsoft OS/2 operating system

Creator:

Pillay, Harish

Abstract:

This thesis discusses an approach whereby Microsoft's MS OS/2 is provided with a means of running the Department of Defense's Transmission Control Protocol/Internet Protocol (TCP/IP). This is done by developing a Packet Protocol Device Driver. This device driver complies with the Packet Driver Specification from FTP Software Inc. and with...

Resource Type:

Masters Thesis

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Academic Affiliation

Electrical and Computer Engineering5

Advisor

Murray, John M.5

Commencement Year

Commencement Year range begin – Commencement Year range end

Current results range from 1988 to 1990

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Committee Member

Herzog, James2
D'Ambrosio, Bruce1
Dietterich, Thomas1
Herzog, Jim1
Levien, Keith1
more Committee Members »

Creator

Ahn, Byoungchul1
Bate, John G.1
Hung, Shih Chuan1
Pillay, Harish1
Skelton, Jeanette K.1

Date

Date range begin – Date range end

Current results range from 1988 to 1990

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Decade

1990-19991
1980-19894

Degree Field

Electrical and Computer Engineering5

Degree Level

Master's4
Doctoral1

Degree Name

Master of Science (M.S.)4
Doctor of Philosophy (Ph.D.)1

Language

English [eng]5

Non-Academic Affiliation

Oregon State University. Graduate School5

Peer Reviewed

No4

Resource Type

Masters Thesis4
Dissertation1

Rights Statement

Copyright Not Evaluated5

Subject

Integrated circuits -- Very large scale integration2
Sorting (Electronic computers)2
Computer network protocols1
Logic circuits1
Neural circuitry -- Computer simulation1
more Subjects »

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