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Filtering by: Creator Hall, Stephen A. Remove constraint Creator: Hall, Stephen A. Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping

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  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    , longer wires have scaled at a slower rate and in some cases have grown larger as chip size and

  • Understanding the ultra-wideband channel within a computer chassis

    Creator:
    Redfield, Stephen J.
    Abstract:
    Recent developments in computing technology have generated a demand for more streamlined and effective test systems. By replacing traditional in-chassis wired interconnects with a broadcast wireless system, fault detection and error susceptibility will drastically improve, input/output capabilities will expand, and routing complexity will decrease. Ultra-wideband impulse radio's (UWB-IR) characteristic multipath-immunity...
    Resource Type:
    Masters Thesis
    Full Text:
    Understanding the Ultra-wideband Channel within a Computer Chassis by Stephen J. Redfield A THESIS submitted

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    12, 2015. Title: The Architecture of a Reusable Built-In Self-Test for Link Training, IO and

  • Spatial motion vector recovery in wireless high definition video transmission using H.264 over WLANs

    Creator:
    Gatimu, Kevin
    Abstract:
    Mobile devices are becoming more prevalent and complex. As a result, the wireless communication aspect of these devices is becoming increasingly significant. At the same time, video demands in terms of availability and quality are also on the uprise. High definition (HD) video is the standard of choice for meeting...
    Resource Type:
    Masters Thesis
    Full Text:
    approved: Ben Lee Mobile devices are becoming more prevalent and complex. As a result, the wireless

  • Methods for evaluating the impact of renewable resource variability on grid operation and planning

    Creator:
    Halamay, Douglas A.
    Abstract:
    With the recent interest in increasing the penetration of renewable energy sources onto the power grid, there has been an unprecedented rapid deployment of wind generation, especially in the US Pacific Northwest. While wind farm developers have continued to expand their operations, power system operators are left to deal with...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Douglas A. Halamay for the degree of Master of Science in Electrical

  • Modeling and analysis of spur structure of digital-to-time conversion based frequency synthesizers

    Creator:
    Talwalkar, Sumit A.
    Abstract:
    Frequency synthesizers are critical components of all communication systems. This thesis considers the issue of undesirable frequency spurs of a relatively recent type of frequency synthesis architecture called digital-to-time conversion (DTC). The DTC-based frequency synthesis architecture has important performance benefits over older frequency synthesizers, such as fast frequency switching, large...
    Resource Type:
    Dissertation
    Full Text:
    ______________________________________________________ AN ABSTRACT OF THE THESIS OF Sumit A. Talwalkar for the degree of Doctor of

  • Side channel attack resistant elliptic curves cryptosystem on multi-cores for power efficiency

    Creator:
    Yoo, Jaewon
    Abstract:
    The Advent of multi-cores allows programs to be executed much faster than before. Cryptoalgorithms use long-bit words thus parallelizing these operations on multi-cores will achieve significant performance improvement. However, not all long-bit word operations in cryptosystems are suitable for parallel execution on multi-cores. In particular, long-bit words used in Elliptic...
    Resource Type:
    Masters Thesis
    Full Text:
    used (which is one of the recommended word size by NIST) on a quad-core with a 32-bit word size

  • Ultra low capacitance RFIC probe

    Creator:
    Jacob, Michael E.
    Abstract:
    In Radio Frequency Integrated Circuits (RFIC) or high frequency digital ICs, there is a demand to probe the internal nodes for testing. The ultra low capacitance RFIC probe presented in his work is a flexible tool for these applications. The probe utilizes the coupling between a tungsten needle and the...
    Resource Type:
    Masters Thesis
    Full Text:
    ICs, there is a demand to probe the internal nodes for testing. The ultra low capacitance RFIC

  • Some contributions to asymmetric error control codes

    Creator:
    Elmougy, Samir
    Abstract:
    In some practical systems, most of the errors are of 1 → 0 type and 0 → 1 errors occur very rarely. In this thesis, first, the capacity of the asymmetric channel is derived. The capacity of the binary symmetric channel (BSC) and the Z-channel can be derived from this...
    Resource Type:
    Dissertation
    Full Text:
    beyond the max- imum designed error detection capability are described. Third, a new class of a

  • Modified VLSI designs for error correction codes

    Creator:
    Chen, Lupin
    Abstract:
    Nowadays, error correction codes have become an integral part in almost all the modern digital communication and storage systems. With the continuously increasing demands for higher speed and lower power communication systems, efficient VLSI implementations of those error correction codes have great importance for practical applications. In this thesis, several...
    Resource Type:
    Masters Thesis
    Full Text:
    (LDPC) codes decoder will be discussed. We propose a low-power memory-efficient Viterbi decoder to