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  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    , longer wires have scaled at a slower rate and in some cases have grown larger as chip size and

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    Papers. IEEE International, 2006, pp. 263–272. [3] M. A. A. Latif, N. B. Z. Ali, and F. A. Hussin, “A

  • A novel linear generator for wave energy applications

    Creator:
    Ernst, Steven George
    Abstract:
    With the increasing effort to identify alternative methods of energy generation, extraction of ocean energy has gathered a large interest. Research and industry have begun considering wave energy as the next new alternative energy. The unique challenges of ocean energy requires a wave energy converter to be both robust and...
    Resource Type:
    Masters Thesis
    Full Text:
    angular force, and alpha represents angular momentum as well as the power of a linear equivalent where F

  • Eager data transfer mechanism for user-level network protocol

    Creator:
    Won, Chulho
    Abstract:
    This dissertation investigates the use of a hardware mechanism called Eager Data Transfer (EDT) for achieving the reduction of communication latency for user-level network protocol. To reach the goal, the dissertation addresses the following research issues. First, the development of a communication system performance evaluation tool called Linux/SimOS is presented....
    Resource Type:
    Dissertation
    Full Text:
    investigates the use of a hardware mechanism called Eager Data Transfer (EDT) for achieving the reduction of

  • Methods for evaluating the impact of renewable resource variability on grid operation and planning

    Creator:
    Halamay, Douglas A.
    Abstract:
    With the recent interest in increasing the penetration of renewable energy sources onto the power grid, there has been an unprecedented rapid deployment of wind generation, especially in the US Pacific Northwest. While wind farm developers have continued to expand their operations, power system operators are left to deal with...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Douglas A. Halamay for the degree of Master of Science in Electrical

  • Variable sampling compensation of networked control systems with delays using neural networks

    Creator:
    Lopez-Echevarria, Daniel
    Abstract:
    In networked control systems (NCS) information or packets usually flow from a sensor or a set of sensors to a remotely located controller. Then the controller processes the received information and sends a series of control commands to the actuators through a communication network which could be either wireless or...
    Resource Type:
    Dissertation
    Full Text:
    usually flow from a sensor or a set of sensors to a remotely located controller. Then the controller

  • Modeling and analysis of spur structure of digital-to-time conversion based frequency synthesizers

    Creator:
    Talwalkar, Sumit A.
    Abstract:
    Frequency synthesizers are critical components of all communication systems. This thesis considers the issue of undesirable frequency spurs of a relatively recent type of frequency synthesis architecture called digital-to-time conversion (DTC). The DTC-based frequency synthesis architecture has important performance benefits over older frequency synthesizers, such as fast frequency switching, large...
    Resource Type:
    Dissertation
    Full Text:
                    LIST OF FIGURES (Continued) Figure Page Figure 4.3 Spectrum for F = (32/33)xFREF using a N = 8

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF John A. Liebert for the degree of Master of Science in Electrical

  • Side channel attack resistant elliptic curves cryptosystem on multi-cores for power efficiency

    Creator:
    Yoo, Jaewon
    Abstract:
    The Advent of multi-cores allows programs to be executed much faster than before. Cryptoalgorithms use long-bit words thus parallelizing these operations on multi-cores will achieve significant performance improvement. However, not all long-bit word operations in cryptosystems are suitable for parallel execution on multi-cores. In particular, long-bit words used in Elliptic...
    Resource Type:
    Masters Thesis
    Full Text:
    used (which is one of the recommended word size by NIST) on a quad-core with a 32-bit word size

  • A multi-bit hybrid DSM over full-scale range without feedback DEM

    Creator:
    Kwon, Sunwoo, 1974-
    Abstract:
    Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
    Resource Type:
    Dissertation
    Full Text:
    IDAC,CT IDAC,DT VREF VREF (a) (b) VO,CT VO,DT tV RE F tI DA C, CT t| V O ,C T| σT εO,CT σT