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  • Performance enhancement techniques for low power digital phase locked loops

    Creator:
    Elshazly, Amr
    Abstract:
    Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate...
    Resource Type:
    Dissertation
    Full Text:
    degree of Doctor of Philosophy in Electrical and Computer Engineering presented on June 18, 2012. Title

  • Highly digital power efficient techniques for serial links

    Creator:
    Inti, Rajesh
    Abstract:
    Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gbps) and be fully integrated. This work discusses enabling techniques...
    Resource Type:
    Dissertation
    Full Text:
    and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit which uses a novel frequency

  • Design techniques for high-performance digital PLLs and CDRs

    Creator:
    Yin, Wenjing
    Abstract:
    Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as leakage, poor analog transistor behavior, process variability, and low supply voltage is a challenging task. To overcome these drawbacks, digital PLLs (DPLLs) have recently emerged...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . 18 2.8 DPLL Linear Model. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.9 Noise transfer

  • A Wide Modulation Range and PVT-Tolerant Spread-Spectrum Modulation Clock Generator

    Creator:
    Sun, Hyuk
    Abstract:
    This dissertation presents a phase domain in-loop-bandwidth spread-spectrum clock generation technique. In this proposed technique, a charge-based discrete-time loop filter is proposed to enable the phase domain in-loop-bandwidth spread-spectrum modulation without a delta-sigma modulator or time-to-digital converter. The in-loop-bandwidth modulation technique maximizes the loop bandwidth to improve phase noise suppression...
    Resource Type:
    Dissertation
    Full Text:
    trade-offs: between reference frequency and spread-spectrum modulation range, and between the spread

  • Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters

    Creator:
    Young, Brian LeRoy
    Abstract:
    In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback...
    Resource Type:
    Dissertation
    Full Text:
    feedback in time-to- digital converters (TDCs) is explored. A prototype phase reference, second-order

  • A digital multiplying delay locked loop for high frequency clock generation

    Creator:
    Uttarwar, Tushar
    Abstract:
    As Moore’s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but...
    Resource Type:
    Masters Thesis
    Full Text:
    1.4GHz output frequency with 1.6ps RMS jitter, 17ps peak-to- peak jitter and -50dbC/Hz reference spurs

  • Energy and area efficient techniques for data converters

    Creator:
    Venkatram, Hariprasath
    Abstract:
    Data converters are ubiquitous building blocks of a signal chain. The rapid increase in communication and connectivity devices presents new avenues for pushing the state of the art analog to digital converters. Techniques for improving resolution, bandwidth, linearity and bit-error rate, while reducing the power, energy and area is the...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.14 Capacitance and Error Voltage vs. ADC Resolution . . . . . . . . . . . . 19 2.15 Pipeline

  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation
    Full Text:
    reference (Fig. 2.5), the overall phase noise can be calculated and 18 shown in Fig. 2.6(b). It is

  • Low power design techniques for high speed pipelined ADCs

    Creator:
    Lingam, Naga Sasidhar
    Abstract:
    Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get...
    Resource Type:
    Dissertation
    Full Text:
    Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.1 Sample and Hold

  • Low noise clocking for high speed serial links

    Creator:
    Brownlee, Merrick
    Abstract:
    As the functionality of digital chips continues to increase dramatically, chip- to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has be- come an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are...
    Resource Type:
    Dissertation
    Full Text:
    Noise Analysis 16 3.3 VCO Phase Noise 18 4. CLOCK AND DATA RECOVERY BASICS 21 4.1 Clock and