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Filtering by: Creator Wenny, David Lee Remove constraint Creator: Wenny, David Lee Degree Field Electrical and Computer Engineering Remove constraint Degree Field: Electrical and Computer Engineering

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  • Designing multimedia extensions for configurable processors

    Creator:
    Zier, David A.
    Abstract:
    The purpose of this thesis is to explore the design of a multimedia extension Instruction Set Architecture (ISA) for a reconfigurable processor. An Extendable Multimedia Module (EM3) was designed as an optional module for X32V. X32V is a prototype configurable processor simulator developed at Oregon State University by John Mark...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF David A. Zier for the degree of

  • The dynamic speculation and performance prediction of parallel loops

    Creator:
    Zier, David A.
    Abstract:
    General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
    Resource Type:
    Dissertation
    Full Text:
    Cascadia Architecture David A. Zier and Ben Lee IEEE Transactions on Parallel and Distributed Systems

  • Interface design and system impact analysis of a message-handling processor for fine-grain multithreading

    Creator:
    Metz, David
    Abstract:
    There appears to be a broad agreement that high-performance computers of the future will be Massively Parallel Architectures (MPAs), where all processors are interconnected by a high-speed network. One of the major problems with MPAs is the latency observed for remote operations. One technique to hide this latency is multithreading....
    Resource Type:
    Masters Thesis
    Full Text:
    -handling processor for fine-grain multithreading AN ABSTRACT OF THE THESIS OF David Metz for the degree

  • Architectural support for multithreading on a 4-way multiprocessor

    Creator:
    Kim, Gwang-Myung
    Abstract:
    The microprocessors will have more than a billion logic transistors on a single chip in the near future. Several alternatives have been suggested for obtaining highest performance with billion-transistor chips. To achieve the highest performance possible, an on-chip multiprocessor will become one promising alternative to the current superscalar microprocessor. It...
    Resource Type:
    Masters Thesis
    Full Text:
    Multithreading on a 4-way Multiprocessor. Abstract approved: ----~-r Ben Lee The microprocessors will have

  • MOS switched-current biquadratic filters

    Creator:
    Lee, Bor
    Abstract:
    A MOS biquadratic (biquad) filter employing the switched-current technique is reported. The circuit uses current-mode processing which can offer wide bandwidth, low voltage operation, and can be implemented with standard CMOS technology. Examples of lowpass, highpass, and bandpass filters are given which illustrate the synthesis procedures and the versatility of...
    Resource Type:
    Masters Thesis
    Full Text:
    , Feb. 1990. (To be published) [5] Ringo W. Lee, Tern S. Fiez, Howard C. Yang and David J. Allstot

  • Cost-Age-Time Data Organized Garbage Collection

    Creator:
    Lee, Dongjun
    Abstract:
    NAND flash based solid state drives (SSDs) require out-of-place updating due to the characteristics of flash memories. In addition, due to the mismatched granularity between read/write and erase operations, a cleaning policy involving garbage collection and wear leveling has to perform data migration incurring high overhead. Another challenge is that...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Dongjun Lee for the degree

  • Distortion analysis of switched-current circuits

    Creator:
    Lee, Wing-sun R.
    Abstract:
    Recently, switched-current circuits have received great attention because they offer potentially better performance in terms of speed, low voltage power supplies, and accuracy in mixed-mode analog-digital signal processing. In this thesis, the distortion characteristics, DC offset and AC gain errors induced by the threshold voltage, channel width, channel length, and...
    Resource Type:
    Masters Thesis
    Full Text:
    ABSTRACT OF THE THESIS OF Wing-sun R. Lee for the degree of Master of Science in Electrical and Computer

  • Network monitoring with focus on HTTP

    Creator:
    Schmid, Andreas
    Abstract:
    Since its introduction in the early 1990s, the quick growth of the World Wide Web (WWW) traffic raises the question of whether past Local Area Network (LAN) packet traces still reflect the current situation or whether they have become obsolete. For this thesis, several LAN packet traces were obtained by...
    Resource Type:
    Masters Thesis
    Full Text:
    presented on May 1, 1998. Title: Network Monitoring with Focus on HTTP. Abstract approved: Ben Lee Since

  • Instruction fetching, scheduling, and forwarding in a dynamic multithreaded processor

    Creator:
    Browning, Adam W.
    Abstract:
    Dynamic multithreaded processors attempt to increase the performance of a single sequential program by dynamically extracting threads from sources such as loop iterations. The scheduling of instructions in such a processor plays a vital role in the amount of thread level parallelism that can be extracted and thus the overall...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Ben Lee Dynamic multithreaded processors attempt to increase the performance of a single

  • Enhancing and profiling the AE32000 cycle accurate embedded processor simulator

    Creator:
    Megarajan, Balaji
    Abstract:
    The AE32000 processor core, developed by Advanced Digital Chips Inc., Korea, is used primarily in the embedded processing environment. The AE32000 simulator models this embedded processor core having high code density. An enhanced simulator was developed to study the performance of the present Instruction Set Architecture after comparison with the...
    Resource Type:
    Masters Thesis
    Full Text:
    and Profiling the AE32000 Cycle Accurate Embedded Processor Simulator Abstract approved: Ben Lee