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Filtering by: Creator Murray, Iain A Remove constraint Creator: Murray, Iain A Degree Level Master's Remove constraint Degree Level: Master's

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  • The design of a reduced instruction set computer using a silicon compiler

    Creator:
    Zhang, Licheng
    Abstract:
    The objective of this thesis is to describe the design and implementation of a VSLI reduced instruction set computer (RISC). The RISC machine constitutes a new style of computer architecture. It differs significantly from the complex instruction set computer architectures (CISC) of the past. RISC architectures are characterized by their...
    Resource Type:
    Masters Thesis
    Full Text:
    The design of a reduced instruction set computer using a

  • The architecture and design of a neural network classifier

    Creator:
    Jiang, Jin
    Abstract:
    The objective of this thesis is to present the architecture and design of a neural network-based pattern classifier. The classifier detects textual characters which have been translated, rotated, and corrupted by noise. This form of pattern classifier differs significantly from traditional pattern classifiers. The neural network architecture used in implementing...
    Resource Type:
    Masters Thesis
    Full Text:
    The architecture and design of a neural network classifier

  • IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology

    Creator:
    Rajanala, Arunkumar V.
    Abstract:
    Typically, a Floating Point processor will be attached to a general-purpose digital computer to extend and enhance its numeric processing capabilities. In this thesis a multiple instruction, multiple data machine for the addition, subtraction, multiplication and division of floating point numbers is presented. The algorithms used have been partitioned to...
    Resource Type:
    Masters Thesis
    Full Text:
    IMPLEMENTED USING SILICON COMPILER TECHNOLOGY Abstract Approved Redacted for Privacy : Dr John Murray

  • Reduced instruction set computer memory architectures

    Creator:
    Widjaja, Stephen
    Abstract:
    This thesis describes the design of a Reduced Instruction Set Computer. Its instruction memory utilizes a unique cache architecture and a two-stage memory pipelining technique. Because of the bandwidth of the 64-bit instruction bus, instruction prefetching is possible and is implemented. The data memory is bridged by a four-way set-associative...
    Resource Type:
    Masters Thesis
    Full Text:
    Redacted for PrivacyAbstract approv John Murray This thesis describes the design of a Reduced Instruction

  • Near-inertial motions off the Oregon coast

    Creator:
    Anderson, Iain
    Abstract:
    Nearly three months of current meter records from five moorings off the Oregon coast taken between October 1977 and January 1978 were analyzed for near-inertial motions. The moorings were located from the midshelf out to the foot of the continental slope, spanning the continental margin. All but two of the...
    Resource Type:
    Masters Thesis
    Full Text:
    showed between a 1 and 6% increase in frequency of the near-inertial peak above f (= 0.0592 cph) in all

  • Preparation of C-14 labeled isopropyl phenylcarbamate

    Creator:
    Murray, Joseph
    Resource Type:
    Masters Thesis
    Full Text:
    PREPARATION OF G].4 LLBßLED IbO PRO PYL PHhNTLCARB.AMATE by J!OEPH MuRRAY A TI8 subraitted to OGO1J

  • The design of a single chip logic state analyzer

    Creator:
    Hung, Shih-chuan
    Abstract:
    This thesis describes the design of a single-chip logic analyzer. The utility of such a chip in measuring and recording digital system parameters is illustrated. Possibilities for future applications of this chip in performance monitoring of computer systems are discussed.
    Resource Type:
    Masters Thesis
    Full Text:
    approved: Redacted for Privacy John M. Murray This thesis describes the design of a single-chip logic

  • The architecture and design of a parallel sorting engine

    Creator:
    Bate, John G.
    Abstract:
    Sorting is typically a compute intensive operation used in many areas of industry. With improved technology, both in the VLSI and CAE areas, we can afford to develop hardware based database computers to move the work load off the main computer. In this thesis the architecture of a VLSI parallel...
    Resource Type:
    Masters Thesis
    Full Text:
    Engine Redacted for Privacy Abstract approved: John . Murray Sorting is typically a compute intensive

  • Douglas-fir bark : characterization of a condensed tannin extract

    Creator:
    Song, Hong-keun
    Resource Type:
    Masters Thesis

  • A model of Arctic Ocean internal waves generated by under-ice topography

    Creator:
    Bowline, Cynthia Marie
    Abstract:
    The energy levels of internal waves observed during the Arctic Internal Wave Experiment (AIWEX), conducted from the drifting pack ice in the Beaufort Sea, increased as the speed of the ice drift increased. The possibility of these waves being generated by moving pack ice with a corrugated under-side is explored...
    Resource Type:
    Masters Thesis
    Full Text:
    of Master of Science in Oceanography presented on June 9, 1988 . Title: A Model of Arctic Ocean