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Filtering by: Subject Memory Remove constraint Subject: Memory Degree Name Master of Science (M.S.) Remove constraint Degree Name: Master of Science (M.S.)

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  • Surprise as reinforcing element in retention

    Creator:
    Gee, Kathleen Frances
    Abstract:
    The purpose of this study was to test the hypothesis that four-year old children would better remember what happened in science experiments, and the basic concepts involved in them, when presentation of the experiments involved an element of surprise. Surprise for this study was considered as a situation in which...
    Resource Type:
    Masters Thesis
    Full Text:
    grounded in the memory system (2, p. 75). SURPRISING items may also have an advantage in remembering

  • Processor memory traffic characteristics for on-chip cache

    Creator:
    Ho, Jeremy Yui Luen
    Abstract:
    The motivation of this research is to study different cache designs for on-chip caches that improve processor performance and at the same time minimize the degradation to system performance caused by an increase in the processor memory traffic. As VLSI technology advances we can have bigger and more complex on-chip...
    Resource Type:
    Masters Thesis
    Full Text:
    Processor memory traffic characteristics for on-chip

  • Investigation of special magnetic memory devices

    Creator:
    Lee, Pedro
    Abstract:
    Three types of magnetic memory elements with emphasis placed on low cost and batch fabrication are investigated. The type I element consists of a wired hole in a strip of Deltamax tape. The type II element uses a stack of magnetic tape instead of the Deltamax. The type III element...
    Resource Type:
    Masters Thesis
    Full Text:
    INVESTIGATION OF SPECIAL MAGNETIC MEMORY DEVICES Abs tract approved t'Major pro'esKor) Three types of magnetic

  • Asymmetric clustering using a register cache

    Creator:
    Morrison, Roger Allen
    Abstract:
    Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
    Resource Type:
    Masters Thesis
    Full Text:
    ROB and Ld/St queue Issue queue size L1 I and D-cache L2 unified cache TLB Memory

  • Signal transfer and gain in magnetic-core circuits

    Creator:
    Landgraf, Richard Clark
    Abstract:
    Because of its characteristics, the square-loop magnetic core can be used as the basic device in a logic system. A magnetomotive force (mmf) which is below the threshold mmf of such a core will cause a negligible, nonpermanent amount of flux change in the core; and information signals can be...
    Resource Type:
    Masters Thesis
    Full Text:
    by Fig. 1 has two stable, easily dis- tinguishable states, namely +4 and -4)r. The core has memory

  • Boosting the preschooler memory for schema-inconsistent, gender-based information

    Creator:
    Forbes, Charles W.
    Abstract:
    For gender-related information, previous studies have shown that children of preschool age are more likely to remember schema-consistent information over schema-inconsistent information. In this study, an attempt was made to boost children's recognition for inconsistent information. In order to do this, children were presented with pictures of both gender-consistent and...
    Resource Type:
    Masters Thesis
    Full Text:
    Boosting the preschooler memory for schema-inconsistent

  • Multithreaded virtual processor on DSM

    Creator:
    An, Ho Seok
    Abstract:
    Modern superscalar processors exploit instruction-level parallelism (ILP) by issuing multiple instructions in a single cycle because of increasing demand for higher performance in computing. However, stalls due to cache misses severely degrade the performance by disturbing the exploitation of ILP. Multiprocessors also greatly exacerbate the memory latency problem. In SMPs,...
    Resource Type:
    Masters Thesis
    Full Text:
    also greatly exacerbate the memory latency problem. In SMPs, contention due to the shared bus

  • Design and implementation of configuration modules in a programmable hardware-assisted cache emulator (PHA$E)

    Creator:
    Chalainanont, Nirut
    Abstract:
    Memory hierarchy design is becoming more important as the speed gap be- tween processor and memory continues to grow. Investigations of memory perfor- mance have typically been conducted using trace-driven emulation, which could take tremendous resources (e.g. long emulation time, large storage requirements for traces, and high overall cost). Recent...
    Resource Type:
    Masters Thesis
    Full Text:
    Emulator (PHA$E) . Abstract approved: Alexandre Ferreira Tenca Memory hierarchy design is becoming more

  • A token caching waiting-matching unit for tagged-token dataflow computers

    Creator:
    Traylor, Roger L.
    Abstract:
    Computers using the tagged-token dataflow model are among the best candidates for delivering extremely high levels of performance required in the future. Instruction scheduling in these computers is determined by associatively matching data-bearing tokens in a Waiting-Matching Unit (W-M unit). At the W-M unit, incoming tokens with matching contexts are...
    Resource Type:
    Masters Thesis
    Full Text:
    caching technique. Using a recently developed CAM memory structure as a base, a token caching scheme is

  • Investigation of bipolar resistive switching in zinc-tin-oxide for resistive random access memory

    Creator:
    Murali, Santosh
    Abstract:
    Resistive random access memory (RRAM) is a non-volatile memory technology based on resistive switching in a dielectric or semiconductor sandwiched between two different metals. Also known as memristors, these devices are potential candidates for a next-generation replacement for flash memory. In this thesis, bipolar resistive switching is reported for the...
    Resource Type:
    Masters Thesis
    Full Text:
    -Oxide for Resistive Random Access Memory Abstract approved: John F. Conley Jr