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Filtering by: Committee Member Hanumolu, Pavan Remove constraint Committee Member: Hanumolu, Pavan Non-Academic Affiliation Oregon State University. Graduate School Remove constraint Non-Academic Affiliation: Oregon State University. Graduate School

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  • Automated model parameter extraction for noise coupling analysis in silicon substrates

    Creator:
    Peterson, Brett
    Abstract:
    An automated method, requiring the fabrication of a small set of test structures, efficiently extracts the coefficients of Z-parameter based macromodels. The extraction approach has been validated for both heavily and lightly doped substrates and can be applied to a variety of technologies. After the parameters of a macromodel have...
    Resource Type:
    Masters Thesis

  • Power efficient analog-to-digital converters using both voltage and time domain information

    Creator:
    Oh, Taehwan
    Abstract:
    As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain...
    Resource Type:
    Dissertation
    Full Text:
    , Prof. Karti Mayaram, and Prof. Pavan Hanumolu for serving as my committee members. Their technical

  • Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters

    Creator:
    Zanbaghi, Ramin
    Abstract:
    There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages...
    Resource Type:
    Dissertation
    Full Text:
    , Professor Pavan Hanumolu, and Professor Kartikeya Mayaram for their guidance on my research. I am grateful

  • Techniques for improving timing accuracy of multi-gigahertz track/hold circuits

    Creator:
    Wang, Jingguang
    Abstract:
    Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result...
    Resource Type:
    Masters Thesis
    Full Text:
    . Un-Ku Moon, Dr. Pavan Hanumolu and Dr. Abdollah Farsoni for their insight suggestions and comments

  • Broadband modeling of on-chip transformers for silicon RFICs

    Creator:
    Rapolu, Kavitha
    Abstract:
    Magnetically coupled passive transformers are increasingly integrated on-chip for various analog and radio frequency (RF) applications including direct current (DC) isolation, impedance transformation/matching, and conversion between single-ended and differential signals. A primary motivation for the on-chip integration of transformers is the overall size reduction and reduced cost. However, the performance...
    Resource Type:
    Masters Thesis
    Full Text:
    my committee. Thanks for being very inspiring. I would like to thank Dr. Pavan Hanumolu for serving

  • Substrate noise coupling in ring oscillator-based phase locked loops

    Creator:
    Shreeve, Robert
    Abstract:
    In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35 μm CMOS process. Since the...
    Resource Type:
    Masters Thesis
    Full Text:
    , Author ACKNOWLEDGEMENTS I am deeply appreciative to Dr. Kartikeya Mayaram, Dr. Pavan Hanamoulu, and

  • Low voltage techniques for pipelined analog-to-digital converters

    Creator:
    Carnes, Joshua Kenneth
    Abstract:
    To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the floating switch dead zone, reduced SNR, and reduced OpAmp performance. This thesis analyzes standard and low voltage design issues for pipelined ADCs and proposes a...
    Resource Type:
    Masters Thesis
    Full Text:
    over my stay at OSU including Dr. Pavan Hanumolu, Dr. Gil-Cho Ahn, Dr. YounJae Kook, Dr. Min-Gyu

  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation
    Full Text:
    . Pavan Kumar Hanumolu for his invaluable technical discussions. I want to thank Prof. Gabor Temes for

  • Noise coupling techniques in multi-cell delta-sigma modulators

    Creator:
    Bonu, Madhulatha
    Abstract:
    High performance multi-cell delta-sigma modulators are a preferred choice in applications which require programmability. Multi-cell delta-sigma modulators with M unit cells provide 10log10(M) SQNR improvement for the same thermal noise and bias power due to the uncorrelated quantization noises of the M unit ADCs. This concept is used in this...
    Resource Type:
    Masters Thesis
    Full Text:
    from them. I thank him for being very understanding and nice to me. I would like to thank Dr. Pavan

  • Design techniques for time based data converters

    Creator:
    Gande, Manideep
    Abstract:
    Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as...
    Resource Type:
    Dissertation
    Full Text:
    members Prof. Karti Mayaram, Prof. Gabor C. Temes, and Prof. Pavan Kumar Hanumolufor for serving on my