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Filtering by: Subject Integrated passive components -- Design and construction Remove constraint Subject: Integrated passive components -- Design and construction Non-Academic Affiliation Oregon State University. Graduate School Remove constraint Non-Academic Affiliation: Oregon State University. Graduate School

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  • Design of compact folded-line RF power dividers

    Creator:
    Lim, Chi-young
    Abstract:
    Embedded passives in multi-layer media have gained importance for offering an attractive solution to the implementation of off-chip passive components in RF and mixed signal circuits, especially for wireless applications. Among the passive devices, power dividers and combiners are extensively used for a host of applications including balanced mixers, phase...
    Resource Type:
    Masters Thesis

  • Enabling metal-fill-aware design of integrated circuits

    Creator:
    Shilimkar, Vikas S.
    Abstract:
    In advanced integrated circuit (IC) processes, the metal fill inserted to meet foundry imposed density requirements degrades the performance of interconnects and passive components which ultimately affects the overall circuit performance. Accounting for this degradation through electromagnetic and equivalent circuit modeling is becoming a critical aspect of IC design. However,...
    Resource Type:
    Dissertation
    Full Text:
    availability of computationally efficient models for component design. As the accurate estimation of passive

  • Embedded passives in a multilayer medium

    Creator:
    Seo, Yongseok, 1958-
    Abstract:
    Recent advances in high density low cost RF and microwave three dimensional integration technologies using LTCC(Low Temperature Cofired Ceramics), laminate and other multilayer hybrid and integrated circuits have increased interest in the design of embedded passive components such as inductors, capacitors and filters. The purpose of this study is to...
    Resource Type:
    Dissertation
    Full Text:
    interest in the design of embedded passive components such as inductors, capacitors and filters. The

  • Low power scheduling schemes that consider latency and resource constraints at multiple voltages

    Creator:
    Huang, Shyh-Sen
    Abstract:
    Power reduction can be achieved at many different levels, such as architecture, algorithm, logic, and transistor levels in circuit design. This thesis focuses on low power scheduling at the algorithm level. We present a latency-constrained scheduling and a latency and resource constrained scheduling, which minimize power consumption for the resources...
    Resource Type:
    Masters Thesis
    Full Text:
    FIGURES Figure Page 1. Design Flow and the Levels of Abstraction

  • Low noise FSCL digital circuits for decimation filter

    Creator:
    Wong, Man Wa
    Abstract:
    A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of...
    Resource Type:
    Masters Thesis
    Full Text:
    filter 42 LIST OF TABLES Table Page 1 Comparison of a 4-bit CLA and 4-bit CSA 16 2 Design

  • Design techniques for clocking high performance signaling systems

    Creator:
    Hanumolu, Pavan Kumar
    Abstract:
    Scaling of CMOS technology has progressed relentlessly for the past several decades. In order for this unprecedented scaling to benefit the performance of large digital systems, the communication bandwidth between integrated circuits (ICs) must scale accordingly. However, interconnect technology does not scale as aggressively, making communication between chips the major...
    Resource Type:
    Dissertation
    Full Text:
    being 3000 miles away and generously shared his vast knowledge on links design. Gu masterfully

  • Model and design of cmos phase-locked loop

    Creator:
    Shum, Daniel K.
    Abstract:
    This thesis will examine the model and design technique of a self-contained analog CMOS Phase-Locked Loop. This system has an adaptable filter and demodulator for an oscillating frequency of up to 1000 KHz and it is programmable by means of an external resistor and capacitor. The first topic to be...
    Resource Type:
    Masters Thesis
    Full Text:
    Model and design of cmos phase-locked loop AN ABSTRACT

  • Switched-current logic for digital circuit design

    Creator:
    Subramanian, Vivek
    Resource Type:
    Masters Thesis
    Full Text:
    . Hodges and G.H. Jackson, Analysis and Design of Digital Integrated Circuits, Mc Graw Hill, 1988. 46

  • The low-power design of prefix adder

    Creator:
    Chang, Che-jen
    Abstract:
    Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area. In...
    Resource Type:
    Masters Thesis
    Full Text:
    index in the design of a 64 bit adder. The carry skip adder is the best one in a design of a 16 and 32

  • Analysis and modeling of single-ended and differential spiral inductors in silicon-based RFICs

    Creator:
    Watson, Adam C.
    Abstract:
    A new comprehensive wide-band compact modeling methodology for single-ended spiral inductors and differential spiral inductors is presented. The new modeling methodology creates an equivalent circuit model consisting of frequency-independent circuit elements for use in circuit simulators. A fast automated extraction procedure is developed for determining the circuit element values from...
    Resource Type:
    Masters Thesis
    Full Text:
    creation of "System on Chip" (SoC) and "Application Specific Integrated Circuits" (ASIC). The SoC design