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Filtering by: Subject Low voltage systems Remove constraint Subject: Low voltage systems Non-Academic Affiliation Oregon State University. Graduate School Remove constraint Non-Academic Affiliation: Oregon State University. Graduate School

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  • An ultra low power frequency reference for timekeeping applications

    Creator:
    Oporta, Hector Ivan
    Abstract:
    An ultra low power crystal oscillator that provides a frequency reference for battery powered timekeeping applications is presented. An amplitude control circuit is employed to ensure that minimum current is consumed. A subthreshold voltage regulator provides a supply voltage for the oscillator with minimum current consumption. The oscillator and regulator...
    Resource Type:
    Masters Thesis
    Full Text:
    follows it. This allows a high battery voltage to be used with this system, while still maintaining a low

  • Design of high-performance pipeline analog-to-digital converters in low-voltage processes

    Creator:
    Myers, Charles Grant
    Abstract:
    Pipeline analog-to-digital converters (ADCs) have long been used in high-speed systems for power-efficient data conversion. Broadband communication and video processing systems are placing high demands on converter accuracy and speed (above 14 bits and in the multiple-MHz range). The increasing converter requirements coupled with lower supply voltages in modern processes...
    Resource Type:
    Masters Thesis
    Full Text:
    : Design of High-Performance Pipeline Analog-to-Digital Converters in Low–Voltage Processes . Abstract

  • Active matrix electroluminescent device power considerations

    Creator:
    Beck, Douglas
    Abstract:
    An active-matrix electroluminescent (AMEL) design tool has been developed for the simulation of AMEL display devices. The AMEL design tool is a software package that simulates AMEL device operation using a lumped parameter circuit model. The lumped parameter circuit model is developed primarily to address AMEL power dissipation issues. The...
    Resource Type:
    Masters Thesis
    Full Text:
    voltage NDMOS transistor breakdown voltage, parasitic capacitance optimization, and development of a low

  • Design and modeling of low-power register file memories

    Creator:
    Donkoh, Eric Kwesi
    Abstract:
    With the evolving popularity of new computing platforms such as Ultrabooks, Tablets, and Smart Phones, and the shift to multi-core computing, power is now the key performance limiter, a departure from the traditional frequency limitation. As such, increasingly low-power design solutions feature prominently in early architectural and design space exploration...
    Resource Type:
    Dissertation
    Full Text:
    design complexities and constraints (power, area, timing, low-voltage operation requirements). Existing

  • Improved design techniques for low-voltage low-power switched-capacitor delta-sigma modulators

    Creator:
    Grilo, Jorge
    Abstract:
    This dissertation investigates the constraints which arise when switched-capacitor (SC) delta-sigma modulators are designed for low-voltage operation, targeting also low power dissipation, and proposes methods of improving the performance and optimizing for low power dissipation. This is accomplished by identifying critical elements whose performance can lead to increased power dissipation,...
    Resource Type:
    Dissertation
    Full Text:
    Improved Design Techniques For Low-Voltage Low-Power Switched

  • A resource-constrained scheduling scheme that considers resources operating at multiple voltages and register assignment

    Creator:
    Lee, Chee
    Abstract:
    Power and timing requirements are becoming more and more stringent as applications move from less mobile devices to more mobile ones. As such, it is important to optimize these applications as much as possible in order to provide the best solution that is low power and low latency. Although there...
    Resource Type:
    Masters Thesis
    Full Text:
    - voltage resources. Nodes with low mobility are given priority when assigning to high-voltage resources

  • Optimizing performance/watt of embedded SIMD multiprocessors through a priori application guided power scheduling

    Creator:
    Albright, Ryan K.
    Abstract:
    A method for improving performance/watt of an embedded single-instruction multiple-data (SIMD) architecture using application-guided a priori scheduling of hardware resources is presented. A multi-core architectural simulator is adopted that accurately estimates power, performance, and utilization of various processor components (logic, interconnect and memory). A greedy search is then performed on...
    Resource Type:
    Masters Thesis
    Full Text:
    ) while operating below the threshold voltage [21]. Because of the low clock frequency requirement

  • Novel structures for high-speed delta-sigma data converters

    Creator:
    Chae, Jeong Seok
    Abstract:
    As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover, the small physical dimensions of transistors allow the placing of many more blocks into a single chip, including highly accurate analog blocks and complicated digital...
    Resource Type:
    Dissertation
    Full Text:
    such as low-distortion [4] and/or noise-coupling [5] topology. In this thesis, novel system and

  • Design techniques for low-power electrical and optical serial link receivers

    Creator:
    Bai, Rui
    Abstract:
    As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links. However, the increase in data-rate is sustainable only if the I/O energy efficiency improves as well. This dissertation explores several techniques to enable high-speed links...
    Resource Type:
    Dissertation
    Full Text:
    efficiency is presented. Low-voltage operation is proven to be an effective way to reduce power consumption

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    through the use of low-voltage swing signaling. A network-on-chip routing architecture is presented that