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Filtering by: Advisor Lu, Shih-Lien Remove constraint Advisor: Lu, Shih-Lien Resource Type Masters Thesis Remove constraint Resource Type: Masters Thesis

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  • A low ground bounce CMOS off-chip driver design

    Creator:
    Zheng, Jieyin
    Abstract:
    With the advancement of technology, submicron CMOSonly process is available now for Application Specific Integrated Circuits (ASICs). The high integration leads to the need for high pin counts. However voltage supply and ground bounce due to many output drivers switching at the same time is becoming a major problem. In...
    Resource Type:
    Masters Thesis
    Full Text:
    approved: ShihLien Lu With the advancement of technology, submicron CMOSonly process is available now for

  • A micro data flow (MDF) : a data flow approach to self-timed VLSI system design for DSP

    Creator:
    Merani, Lalit T.
    Abstract:
    Synchronization is one of the important issues in digital system design. While other approaches have been intriguing, up until now a globally clocked timing discipline has been the dominant design philosophy. However, we have reached the point, with advances in technology, where other options should be given serious consideration. VLSI...
    Resource Type:
    Masters Thesis
    Full Text:
    professor Dr. Shih-Lien Lu. His contribution to this thesis is irreplaceable (most of the ideas were his

  • Micro data flow processor design

    Creator:
    Chang, Chih-ming
    Abstract:
    Computer has evolved rapidly during the past several decades in terms of its implementation technology; it's architecture, however, has not changed dramatically since the von Neumann computer(control flow) model emerged in the 1940s. One main reason is that the performance for this kind of computers was able to satisfy the...
    Resource Type:
    Masters Thesis
    Full Text:
    presented on September 24. 1993. Title: Micro Data Flow Processor Design Abstract approved: ShihLien Lu

  • Design of a 80/250-Msample/s FIR-filter for a pipelined ADC-FIR interface

    Creator:
    Stier, Hubert J.
    Resource Type:
    Masters Thesis
    Full Text:
    /250-Msample/s FIR-Filter for a Pipe lined ADC-FIR Interface. Abstract approved: Shih-Lien Lu With

  • Design of a True-Q Flip Flop

    Creator:
    Hui, Henry
    Abstract:
    A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as an asynchronous storage element in micropipelines or a part of the synchronizer. It is capable of double-edge triggering which latches data at both the rising and the trailing edges. It is also free of the...
    Resource Type:
    Masters Thesis
    Full Text:
    presented on October 20. 1994. Title: A Design of True-0 Flip Flop Abstract approved: Shih-Lien Lu A CMOS

  • Efficient arithmetic using self-timing

    Creator:
    Ramachandran, Ravichandran
    Abstract:
    The recent advances in VLSI technology have facilitated feature shrinking and hence a rapid increase in the levels of integration at the chip level. This increase in the level of integration has brought along with it a host of other constraints, the most crucial being timing management and increased power...
    Resource Type:
    Masters Thesis
    Full Text:
    : Efficient Arithmetic Using Self-timing Abstract approved: Shih-Lien Lu The recent advances in VLSI

  • Design and performance estimation of two-dimensional discrete cosine transform

    Creator:
    Li, Quanrong
    Abstract:
    A VLSI system for image compression based on two dimensional discrete cosine transform (2-D DCT) is designed and its performance is estimated. The focus is mainly on the reduction of power consumption and a reasonable speed. A 2-D DCT algorithm called row-column decomposition is chosen for the VLSI design of...
    Resource Type:
    Masters Thesis
    Full Text:
    of Twodimen­ sional Discrete Cosine Transform Abstract approved: ShihLien Lu A VLSI system for

  • High speed digital FIR filter design

    Creator:
    Zhou, Bo
    Abstract:
    The objective of this thesis is to design a high speed digital FIR filter. The inputs of the system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which...
    Resource Type:
    Masters Thesis
    Full Text:
    December 2, 1996. Title: High Speed Digital FIR Filter Design Abstract approved: Shih_Lien Lu The

  • Failure analysis of Muller-C-element

    Creator:
    Chew, Oonpin
    Abstract:
    Asynchronous circuits have recently been a breakthrough in many high performance computers. The concept of asynchronous circuits which started a long time ago has slowly grasped the attention of many designers. The Muller-C-element is an important control block in many asynchronous designs and therefore it is important to understand some...
    Resource Type:
    Masters Thesis
    Full Text:
    education here in Oregon State University (United States of America). Special thanks to Dr. Shih-Lien Lu

  • Interlaced instruction window

    Creator:
    Ong, Wee-Shong
    Abstract:
    A relatively recent development in the late 1980s in processors has been the superscalar processor. Superscalar processors use multiple pipelines in an attempt to achieve higher performance than previous generations of processors. Having multiple pipelines makes it possible to execute more than one instruction per cycle. However, since instructions are...
    Resource Type:
    Masters Thesis
    Full Text:
    on May 27 1997. Title: Interleaved Instruction Window. Abstract approve Shih-Lien Lu A