The purpose of this study was to test the hypothesis that four-year
old children would better remember what happened in science
experiments, and the basic concepts involved in them, when presentation
of the experiments involved an element of surprise. Surprise
for this study was considered as a situation in which...
This experiment used a choice recognition time task. The subjects task was to decide whether a probe tone was or was not among a presented set of one to four tones. One of three cue conditions occured on each trial: the cue (a light) was presented immediately following the tone...
The motivation of this research is to study different cache designs for on-chip
caches that improve processor performance and at the same time
minimize the degradation to system performance caused by an increase in
the processor memory traffic. As VLSI technology advances we can have
bigger and more complex on-chip...
Three types of magnetic memory elements with emphasis
placed on low cost and batch fabrication are investigated.
The type I element consists of a wired hole in a strip of
Deltamax tape. The type II element uses a stack of magnetic
tape instead of the Deltamax. The type III element...
Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
Because of its characteristics, the square-loop magnetic core
can be used as the basic device in a logic system. A magnetomotive
force (mmf) which is below the threshold mmf of such a core will
cause a negligible, nonpermanent amount of flux change in the core;
and information signals can be...
For gender-related information, previous studies have shown that children of
preschool age are more likely to remember schema-consistent information
over schema-inconsistent information. In this study, an attempt was made to
boost children's recognition for inconsistent information. In order to do this,
children were presented with pictures of both gender-consistent and...
Modern superscalar processors exploit instruction-level parallelism (ILP) by issuing multiple instructions in a single cycle because of increasing demand for higher performance in computing. However, stalls due to cache misses severely degrade the performance by disturbing the exploitation of ILP. Multiprocessors also greatly exacerbate the memory latency problem. In SMPs,...
Memory hierarchy design is becoming more important as the speed gap be- tween processor and memory continues to grow. Investigations of memory perfor- mance have typically been conducted using trace-driven emulation, which could take tremendous resources (e.g. long emulation time, large storage requirements for traces, and high overall cost). Recent...
Computers using the tagged-token dataflow model are among the best candidates for delivering extremely high levels of performance required in the future. Instruction scheduling in these computers is determined by associatively matching data-bearing tokens in a Waiting-Matching Unit (W-M unit). At the W-M unit, incoming tokens with matching contexts are...