Search Constraints

Start Over
Filtering by: Subject Switched capacitor circuits -- Design and construction Remove constraint Subject: Switched capacitor circuits -- Design and construction Rights Statement Copyright Not Evaluated Remove constraint Rights Statement: Copyright Not Evaluated

Search Results

  • Embedded passives in a multilayer medium

    Creator:
    Seo, Yongseok, 1958-
    Abstract:
    Recent advances in high density low cost RF and microwave three dimensional integration technologies using LTCC(Low Temperature Cofired Ceramics), laminate and other multilayer hybrid and integrated circuits have increased interest in the design of embedded passive components such as inductors, capacitors and filters. The purpose of this study is to...
    Resource Type:
    Dissertation
    Full Text:
    circuit as well as electromagnetic models have been used to analyze and design these structures. In this

  • Low noise FSCL digital circuits for decimation filter

    Creator:
    Wong, Man Wa
    Abstract:
    A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of...
    Resource Type:
    Masters Thesis
    Full Text:
    filter 42 LIST OF TABLES Table Page 1 Comparison of a 4-bit CLA and 4-bit CSA 16 2 Design

  • Reaction kinetics and mass transport in the electroless deposition of copper

    Creator:
    Ninosky, Joseph M.
    Resource Type:
    Masters Thesis
    Full Text:
    and Mass Transport in the Electroless Deposition of Copper. Milo Koretsky Electroless copper

  • Switched-current logic for digital circuit design

    Creator:
    Subramanian, Vivek
    Resource Type:
    Masters Thesis
    Full Text:
    Switched-current logic for digital circuit design AN

  • Model and design of cmos phase-locked loop

    Creator:
    Shum, Daniel K.
    Abstract:
    This thesis will examine the model and design technique of a self-contained analog CMOS Phase-Locked Loop. This system has an adaptable filter and demodulator for an oscillating frequency of up to 1000 KHz and it is programmable by means of an external resistor and capacitor. The first topic to be...
    Resource Type:
    Masters Thesis
    Full Text:
    LOW-PASS FILTER 10 3.4 LOCK AND CAPTURE RANGES 13 CHAPTER 4 CIRCUIT DESCRIPTION AND DESIGN

  • VLSI implementation of adaptive BIT/serial IIR filters

    Creator:
    Badyal, Rajeev
    Abstract:
    A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal...
    Resource Type:
    Masters Thesis
    Full Text:
    communication and control structures of these arrays offer a substantial advantage for the VLSI design and

  • The low-power design of prefix adder

    Creator:
    Chang, Che-jen
    Abstract:
    Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area. In...
    Resource Type:
    Masters Thesis
    Full Text:
    dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit

  • Device characterization and analog circuit design for heterojunction FETs

    Creator:
    Wang, Binan
    Abstract:
    Present day data processing technology requires very high speed signal processing and data conversion rates. Traditionally, these circuits have been implemented in silicon MOS technology, whose high speed performance is limited, due to inherent material properties. Though relatively immature compared to silicon technology, GaAs integrated circuit technology appears to be...
    Resource Type:
    Masters Thesis
    Full Text:
    Device Characterization and Analog Circuit Design for

  • Characterization of a digital phase locked loop and a stochastic time to digital converter

    Creator:
    Geissenhainer, Erik D.
    Abstract:
    A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited...
    Resource Type:
    Masters Thesis
    Full Text:
    4.6. Delay and slew control circuit schematic

  • A low ground bounce CMOS off-chip driver design

    Creator:
    Zheng, Jieyin
    Abstract:
    With the advancement of technology, submicron CMOSonly process is available now for Application Specific Integrated Circuits (ASICs). The high integration leads to the need for high pin counts. However voltage supply and ground bounce due to many output drivers switching at the same time is becoming a major problem. In...
    Resource Type:
    Masters Thesis
    Full Text:
    2.3 Prolong the Rise and Fall Time 7 Chapter 3. Proposed Circuit Design 10 3.1 Introduction 10 3.2