Index Catalog // ScholarsArchive@OSU

Wirelessly Powered cm-Scale Sensor for Small Insect Localization Application

Creator:: Kang, Jian
Abstract:: The prevalence of Internet-of-Things (IoT) applications leads to an increasing focus on the design and optimization of sensor nodes. Battery lifetime and associated costs of battery replacement often limits the long term operation and viability of sensor nodes. RF wireless energy harvesting on the other hand can be appealing since...
Resource Type:: Dissertation

Design of 28 GHz Low-Power Phased-Array Receiver Frontend in CMOS

Creator:: Garg, Robin
Abstract:: This work presents the design and implementation of a low power phased-array receiver frontend at 28 GHz in 65 nm CMOS. The frontend incorporates a low- power low-noise amplifier(LNA) and a passive reflection-type phase shifter (RTPS) capable of providing 360° phase shift with 5-bit phase resolution and low loss variation....
Resource Type:: Masters Thesis

High-Resolution mm-wave Digitally Controlled Oscillator in CMOS

Creator:: Wang, Yunqi
Abstract:: All-digital PLLs promise flexible and precise frequency modulation continous-wave(FMCW) radar signal signal for 77GHz radar applications. Such PLLs require digitally-controlled oscillators(DCO) with wide frequency tuning range and high resolution to address a range of applications and low phase noise requirements. In this thesis, novel resonator structures with ne capacitance/inductance switching...
Resource Type:: Masters Thesis

Analysis and design on low-power short-range radios for wireless body area networks

Creator:: Cheng, Jiao
Abstract:: The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die area are some of the most important criteria for successful WBAN implementations. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in...
Resource Type:: Dissertation

Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs

Creator:: Chow, Andrew Siv-Anne
Abstract:: The new CMOS folded source-coupled logic (FSCL) technique intended for mixed-mode integrated circuits has been designed. It has advantages over conventional CMOS circuit in terms of reduced current spike, circuit delay, logic flexibility, and layout density. A simple CPU implemented in 2 μm CMOS technology with a 5.0 volt supply...
Resource Type:: Masters Thesis

Energy efficient communication across on-chip wires in digital CMOS

Creator:: Postman, Jacob
Abstract:: For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
Resource Type:: Dissertation

Design techniques for time based data converters

Creator:: Gande, Manideep
Abstract:: Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as...
Resource Type:: Dissertation

Fully-differential current-mode CMOS circuits and applications

Creator:: Zele, Rajesh H.
Abstract:: With increasing interest in current-mode analogue processing due to its high performance properties such as speed, bandwidth and accuracy compared to voltage-mode processing, new current-mode alternatives to various conventional circuit designs are appearing. In this report, a novel circuit design to construct a fully-differential current-mode operational amplifier ( OP-AMP )...
Resource Type:: Masters Thesis

Current-feedthrough cancellation techniques in switched-current circuits

Creator:: Lao, Paul A.
Resource Type:: Masters Thesis

A token caching waiting-matching unit for tagged-token dataflow computers

Creator:: Traylor, Roger L.
Abstract:: Computers using the tagged-token dataflow model are among the best candidates for delivering extremely high levels of performance required in the future. Instruction scheduling in these computers is determined by associatively matching data-bearing tokens in a Waiting-Matching Unit (W-M unit). At the W-M unit, incoming tokens with matching contexts are...
Resource Type:: Masters Thesis

ScholarsArchive@OSU

Wirelessly Powered cm-Scale Sensor for Small Insect Localization Application

Design of 28 GHz Low-Power Phased-Array Receiver Frontend in CMOS

High-Resolution mm-wave Digitally Controlled Oscillator in CMOS

Analysis and design on low-power short-range radios for wireless body area networks

Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs

Energy efficient communication across on-chip wires in digital CMOS

Design techniques for time based data converters

Fully-differential current-mode CMOS circuits and applications

Current-feedthrough cancellation techniques in switched-current circuits

A token caching waiting-matching unit for tagged-token dataflow computers

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