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Filtering by: Subject Programmable array logic

Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification

Creator:

Gilbert, John D.

Abstract:

Minimizing the number of product terms in a PLA implementation is a large step towards saving area on a VLSI chip using PLA logic. Due to the large amounts of computer time necessary to achieve this minimization, a number of heuristic approaches have been developed to provide near-optimal solutions in...

Resource Type:

Masters Thesis
Dynamically configurable systolic arrays

Creator:

Durgam, Jaisimha K.

Abstract:

Digital signal and image processing and other real time applications involve simple but large amounts of computations. These problems have an enormous amount of inherent parallelism and demand high speed computation. Conventional computers do not possess these characteristics and this had led to the development of new architectural concepts. Among...

Resource Type:

Masters Thesis