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Filtering by: Subject Simultaneous multithreading processors Remove constraint Subject: Simultaneous multithreading processors

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Analysis of the effectiveness of multithreading for interrupts on communication processors

Creator:

Pattery, Vinu J.

Abstract:

High bandwidth of networks demands high performance communication processors that integrate application processing, network processing, and system support functions into a single, low cost System-On-Chip (SOC) solution. However, conventional processors, when used in network related applications, are beset by the overhead of save/restore of register context, cache misses due to...

Resource Type:

Masters Thesis
The dynamic speculation and performance prediction of parallel loops

Creator:

Zier, David A.

Abstract:

General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...

Resource Type:

Dissertation
Instruction fetching, scheduling, and forwarding in a dynamic multithreaded processor

Creator:

Browning, Adam W.

Abstract:

Dynamic multithreaded processors attempt to increase the performance of a single sequential program by dynamically extracting threads from sources such as loop iterations. The scheduling of instructions in such a processor plays a vital role in the amount of thread level parallelism that can be extracted and thus the overall...

Resource Type:

Masters Thesis
Dependency speculation in dynamic simultaneous multi-threading

Creator:

Nelson, Jarrod A.

Abstract:

The purpose of this thesis is to explore dependency speculation in Dynamic Simultaneous Multi-Threading (DSMT). DSMT is a microprocessor architecture which attempts to extract Thread Level Parallelism (TLP) from single-threaded programs at run-time. This is accomplished by running multiple iterations of program loops in parallel. The DSMT architecture was originally...

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Masters Thesis

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Academic Affiliation

Electrical Engineering and Computer Science3
Electrical and Computer Engineering1

Advisor

Lee, Ben3
Lee, Il Beom1

Commencement Year

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Current results range from 2003 to 2009

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Committee Member

Nguyen, Thinh2
Traylor, Roger2
Bose, Bella1
Levien, Keith L.1
Lucchese, Luca1
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Browning, Adam W.1
Nelson, Jarrod A.1
Pattery, Vinu J.1
Zier, David A.1

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Current results range from 2003 to 2009

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2000-20094

Degree Field

Electrical and Computer Engineering4

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Master's3
Doctoral1

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Master of Science (M.S.)3
Doctor of Philosophy (Ph.D.)1

File Format

application/pdf2

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English [eng]4

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All rights reserved3

Non-Academic Affiliation

Oregon State University. Graduate School4

Peer Reviewed

No3

Resource Type

Masters Thesis3
Dissertation1

Rights Statement

In Copyright3
Copyright Not Evaluated1

Subject

Simultaneous multithreading processors[remove]4
Computer architecture1
Computer scheduling1
Interrupts (Computer science)1
Parallel programming (Computer science)1
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