An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves
the swing of a Colpitts VCO by allowing the signal to swing below ground and above the
supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates
at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different...
The design of mobile wireless devices has always focused on reducing power, area, and cost. This dissertation proposes two techniques that are leveraged to save power and area and therefore cost. The first techniques reduces the noise in the receiver and results in a relaxed power requirement. The second technique...
Delay insensitive asynchronous circuitry provides significant advantages with
respect to substrate noise due to localized switching. The differences between the
substrate noise from NULL Convention Logic (NCL) and traditional Clocked
Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
Wireless sensor networks are becoming important in several monitoring and sensing applications. Ultra low power consumption in the sensor nodes is important for extending the battery life of the nodes. In this dissertation, two low power BFSK receiver architectures are proposed and verified with prototype implementations in silicion.
A 2.4...
The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in
environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
Low noise oscillators are universally needed in digital systems for clock generation and synchronization, and in radio-frequency communication front-ends for frequency up- and down-conversion. Noise in oscillators results in timing jitter, and limits the clock frequency of digital systems. In radio-frequency communication systems, phase noise in oscillators lowers the signal-to-noise...